– 59 –
TV ANT
Q162
1ST
VIDEO
11
45
38
40
Q8065
BUFFER
C
Y
Y
C
IC301
COMB
FILTER
K1051
S1 IN
LPF
Y-PIP
PIP CVBS IN
DATA
CLK
Q343
BAND
PASS
SW
VIDEO
DET.
K1002
V2 IN
10
47
1
42
44
43
Q202
BUFFER
Q306
BUFFER
INPUT
FILTER
Q307
BUFFER
4
15
13
Q1071
BUFFER
BAND PASS
FILTER
Q342
BUFFER
Q341
BUFFER
Q216
INVERT.
BUS
Interface
Y in
C in
C-PIP
IC101
SIGNAL PROCESSOR
IC8001
PIP SIGNAL PROCESSOR
ACK
Q8097
BUFFER
Q8093
BUFFER
Q8090
BUFFER
Q8076
BUFFER
INPUT
FILTER
Q8073
BUFF.
BUS SCL
34
TV/AV
8
BUS SDA
32
IC801
CPU
S1-SW
12
MAIN AV1/AV2
5
PIP TV/AV
7
PIP AV1/AV2
6
MAIN S SELECT
4
A101
TUNER
+9V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
H
L
H
L
H
L
IC1001
S1/V1/V2
SWITCH
R1027
+9V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
H
L
H
L
H
L
IC1002
PIP
COMPO.
VIDEO
SWITCH
R1041
+9V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
H
L
H
L
H
L
IC1081
MAIN
S1/V1/V2
SWITCH
R1082
K1001
V1 IN
Q1093,
Q1094,
Q1096
R1007
C1
C1
Y1
V1
R1042
C
C
Y
R1081
C1
C(COMB)
EXT.V
Y
Y(COMB)
Q332
BUFFER
YC
MIX
V2
EXT V IN
INT V FOR PIP
49
Sync tip
Clamp
51
xx
xx
25
23
13
14
40
39
37
38
8
24
9
15
10
Bias
15
3
I
2
C
I/F
V-chip
data slicer
Sync tip
Clamp
A/D
8bit
Y/C SEP
(LPF, BPF)
Phase
Select
HD
D/A
8bit
D/A
8bit
Delay
(I
2
C)
HPLL
4
fsc
Delay
Encode 4
fsc
MIX
Level
Detect
Burst Data
Sampling
A/D
8bit
Bias
Luma
Clamp
Sync
Sep
Demod
Y
C
Phase
Detect
AFC
Tint
Timing Gen
(Decode)
Delay
6
R–Y
6
B–Y
6
Y
Vert-filter
&
Multiplexer
RAM (1H)
LPF
&MPY
Delay
6
Y
Demultiplex
6 R–Y
6 B–Y
RAM
96Kbits
Y
B–Y
R–Y
VCXO
Driver
Lock/Free-run
via I
2
C
4
fsc
Bias
Back Porch
Clamp
Timing Gen
(Memory
Cont)
VCXO
47
45
43
41
34
33
32
4
5
3
2
21
22
20
17
30
28
29
31
Vdd/Vss
for test
Vrt (s)
Vrb (s)
ADJ-Ysub
Yout-sub
Cout-sub
ADJ-Csub
Vin (m)
Vrt (m)
Vrb (m)
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
SWM
/TEST4
BGP(s)
/TEST0
CSYNC(s)
/TEST1
SCK
C-PIPin
Y-PIPin
SWMG
/TEST7
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
BIAS
VCXO in
VCXO out
PIP Signal Processor and TV/AV Switching Circuit
