COMe-cTL6 – User Guide Rev. 1.7
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Sub-Screen
Function
Second level Sub-Screen/Description
CPU
Configuration>
AES
[Enabled, Disabled]
RaceConditionResponse
Policy
[Enabled, Disabled]
Power &
Performance>
CPU Power Management
Control>
Boot performance
mode
[Max Battery, Max Non-Turbo
Performance, Turbo Performance]
Intel SpeedStep ™
Allows more than two frequency ranges
to be supported.
[Enabled, Disabled]
Intel Speed Shift
Technology
Enable exposes CPPC v2 interface to allow
for hardware controlled p-states.
[Enabled, Disabled]
Per Core P State
OS control mode
Disable set Bit 31 =1 command 0x06. When
set the highest core request is used for all
other core requests.
[Enabled, Disabled]
HwP Autonomous
Per Core P State
Disable requests the same value for all
cores all the time.
[Enabled, Disabled]
HwP Autonomous
EPP Grouping
Autonomous will not necessarily request
same values for all cores with same EPP.
[Enable, Disabled]
EPB override over
PECI
Enable by sending pcode command 0x2b,
subcommand 0x3 to 1. This allows OOB
EPB PECI override control.
[Enable, Disabled]
HwP Fast MSR
Support
Support for IA32_HWP_REQUEST MSR
[Enabled, Disabled]
Turbo Mode
Note: Requires EMTTM to be enabled.
AUTO means enabled.
[Enabled, Disabled]
View/Configure
Turbo Options>
Read only field
Current Turbo Settings: Max Turbo Power
Limit, Min Turbo Power Limit, Package TDP
Limit, Power Limit 1 / 2 and 1 to 64
Core Turbo Ratio Limit Ratio. (TRLR).
Energy Efficient
P-State
[Enabled, Disabled]
Package Power
Limit MSR
Enable to lock. A
reset is required to
unlock the register.
[Enabled, Disabled]
1-Core Turbo Ratio Limit Ration (TRLR)
Override [41]
2-Core Turbo Ratio Limit Ration (TRLR)
Override [41]
3-Core Turbo Ratio Limit Ration (TRLR)
Override [39]
