Samsung YP-R1, Service Manual

Page: 36 / 69

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1
2
1
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Samsung Electronics 4-21
Troubleshooting
GND
FM_LINE_IN_L
FM_LINE_IN_R
R117
1K
R116
1K
C
11
8
10
nF
C
11
9
10
nF
32.768KHZ_OUT
C
11
4
10
0n
F
GND
GND
FM_BUS_EN
FM_ANT
I2C_CLK0
I2C_DAT0
GND
GND
GND
32.768KHZ_OUT
P_3.0V
GND
C
10
7
10
0n
F
GND
P_1.8V
REG_BT
GND
R105
1K
BT_WAKE
BT_RST
AUD_DATA_IN
REG_BT
REG_BT
GND
GND
GND
GND
BT_UART_RX0
BT_UART_TX0
AUD_LRCK
AUD_BCLK
L101
8.2nH
B
10
1
60
0o
hm
BT_UART_RTS0
BT_UART_CTS0
R
10
2
10
0K
C111
100nF
FM_SEARCH
P_3.0V
C110 0.1nF
ANT101
ODBTPTR3015
1
2
3
4
C
12
3
10
0n
F
R107
15K
R101
47K
R
10
8
47
K
C
10
5
10
00
nF
C
10
6
10
00
nF
U101
SI4709-B-GMR
1
NC_1
2
FMI
3
RFGND
4
RST
5
S
E
N
6
S
C
LK
7
S
D
IO
8
V
IO
9
RCLK
10
VD
11
GND_1
12
ROUT
13
LO
U
T
14
V
A
15
G
P
O
16
N
C
_2
17
G
N
D
_2
AUD_DATA_OUT
U102
BCM2070CB0KUFBXG
G4
RES
D1
RFP
G2
XIN
G3
XOUT
A4
LPO_IN
B2
REG_EN
A3
VBAT
A2
VREGHV
A1
VREG
B4
RST_N
C4
TM0
F3
TM2
B5
GPIO_0
B3
GPIO_1
E6
GPIO_5
E3
GPIO_6
B7
GPIO_7
D8
UART_RXD
C8
UART_TXD
D7
UART_RTS_N
E8
UART_CTS_N
F7
SCL
E7
SDA
A8
SPIM_CLK
C7 SPIM_CS_N
F6 PCM_IN
G6
PCM_OUT
F4
PCM_CLK
F5 PCM_SYNC
B6 COEX_IN
E4 COEX_OUT0
E5 COEX_OUT1
B1 VDDIF
C1 VDDTF
E1
VDDLNA
F1
VDDRF
G1 VDDPX
A5 VDDC_1
B8 VDDC_2
F8
VDDC_3
G5
VDDO_1
A6 VDDO_2
G8 VDDO_3
C2 VSS_1
D2 VSS_2
F2
VSS_3
D3
VSS_4
C6 VSS_5
A7 VSS_6
G7 VSS_7
GND
BT_REG_EN
C121
2200nF
C122
2200nF
R
10
3
10
0K
R
11
1
10
0K
R118
1K
C
12
0
47
00
nF
R
11
5
10
0K
C
12
5
10
nF
C
12
4
10
nF
C
10
3
10
nF
C
11
5
10
nF
C
11
2
10
nF
GND
R113
150
R114
150
C
12
6
10
0n
F
X101
26.00MHz
1
2
3 4
C
11
7
10
0n
F
C
10
2
0.
00
82
nF
C
10
1
0.
00
82
nF
F101
2450MHz
1
GND_1
2 OUT
3
GND_2
4
IN
C
11
6
0.
01
5n
F
C
11
3
0.
01
5n
F
C108
0.1nF
C
10
4
0.
00
2n
F
15K
1% OK
For impedance matching
CONNECT PIN 1 AND PIN 4
close to
VD pin
FMI trace as
short as possible
C116 Should be placed
close to VDDTF(C1)PIN.
close to VDDPX(G1)/VDDIF(B1)PIN.
C112/C124 Should be placed
close to VDDLNA(E1)PIN.
C113 Should be placed
NC
NC

BLUETOOTH / FM, page 7-9
GND
FM_LINE_IN_L
FM_LINE_IN_R
R117
1K
R116
1K
C
11
8
10
nF
C
11
9
10
nF
32.768KHZ_OUT
C
11
4
10
0n
F
GND
GND
FM_BUS_EN
FM_ANT
I2C_CLK0
I2C_DAT0
GND
GND
GND
32.768KHZ_OUT
P_3.0V
GND
C
10
7
10
0n
F
GND
P_1.8V
REG_BT
GND
R105
1K
BT_WAKE
BT_RST
AUD_DATA_IN
REG_BT
REG_BT
GND
GND
GND
GND
BT_UART_RX0
BT_UART_TX0
AUD_LRCK
AUD_BCLK
L101
8.2nH
B
10
1
60
0o
hm
BT_UART_RTS0
BT_UART_CTS0
R
10
2
10
0K
C111
100nF
FM_SEARCH
P_3.0V
C110 0.1nF
ANT101
ODBTPTR3015
1
2
3
4
C
12
3
10
0n
F
R107
15K
R101
47K
R
10
8
47
K
C
10
5
10
00
nF
C
10
6
10
00
nF
U101
SI4709-B-GMR
1
NC_1
2
FMI
3 RFGND
4
RST
5
S
E
N
6
S
C
LK
7
S
D
IO
8
V
IO
9
RCLK
10
VD
11
GND_1
12
ROUT
13
LO
U
T
14
V
A
15
G
P
O
16
N
C
_2
17
G
N
D
_2
AUD_DATA_OUT
U102
BCM2070CB0KUFBXG
G4
RES
D1
RFP
G2
XIN
G3
XOUT
A4
LPO_IN
B2
REG_EN
A3
VBAT
A2
VREGHV
A1
VREG
B4
RST_N
C4
TM0
F3
TM2
B5
GPIO_0
B3
GPIO_1
E6
GPIO_5
E3
GPIO_6
B7
GPIO_7
D8
UART_RXD
C8
UART_TXD
D7
UART_RTS_N
E8
UART_CTS_N
F7
SCL
E7
SDA
A8
SPIM_CLK
C7 SPIM_CS_N
F6 PCM_IN
G6 PCM_OUT
F4 PCM_CLK
F5
PCM_SYNC
B6
COEX_IN
E4 COEX_OUT0
E5 COEX_OUT1
B1
VDDIF
C1
VDDTF
E1 VDDLNA
F1 VDDRF
G1 VDDPX
A5 VDDC_1
B8
VDDC_2
F8
VDDC_3
G5 VDDO_1
A6 VDDO_2
G8 VDDO_3
C2
VSS_1
D2
VSS_2
F2 VSS_3
D3 VSS_4
C6 VSS_5
A7 VSS_6
G7
VSS_7
GND
BT_REG_EN
C121
2200nF
C122
2200nF
R
10
3
10
0K
R
11
1
10
0K
R118
1K
C
12
0
47
00
nF
R
11
5
10
0K
C
12
5
10
nF
C
12
4
10
nF
C
10
3
10
nF
C
11
5
10
nF
C
11
2
10
nF
GND
R113
150
R114
150
C
12
6
10
0n
F
X101
26.00MHz
1 2
3 4
C
11
7
10
0n
F
C
10
2
0.
00
82
nF
C
10
1
0.
00
82
nF
F101
2450MHz
1
GND_1
2 OUT
3
GND_2
4
IN
C
11
6
0.
01
5n
F
C
11
3
0.
01
5n
F
C108
0.1nF
C
10
4
0.
00
2n
F
15K
1% OK
For impedance matching
CONNECT PIN 1 AND PIN 4
close to
VD pin
FMI trace as
short as possible
C116 Should be placed
close to VDDTF(C1)PIN.
close to VDDPX(G1)/VDDIF(B1)PIN.
C112/C124 Should be placed
close to VDDLNA(E1)PIN.
C113 Should be placed
NC
NC

BLUETOOTH / FM, page 7-9
CON901
CON601
CON802
CON801
U503 U502
U301
U102
U601
U501

MAIN PCB Bottom, page 6-3
<Fig. 4-11>