AT INTERFACE and ATA COMMANDS
6-
24 WA31273A / WA32543A / WA33203A / WA3216A / WA31083A / WA32162A
6-4-4-15 Word 56 : Number of current logical sectors per logical track
The number of user-addressable logical sectors per logical track in the current
translation mode.
6-4-4-16 Word 57-58 : Current capacity in sector
The current capacity in sectors excludes all sectors used for device-specific purposes.
The value reported in this field shall be the product of words 54, 55 and 56.
6-4-4-17 Word 59 : Multiple sector setting
If the valid bit is set, then bits 7-0 reflect the number of sectors currently set to transfer
on a Read/Write Multiple command. If word 47 bits 7-0 are zero then word 59 bits 8-0
shall also be zero.
6-4-4-18 Word 60-61 : Total number of user addressable sectors
If the device supports LBA Mode, these words reflect the total number of user
addressable sectors. This value does not depend on the current device geometry. If the
device does not support LBA mode, these words shall be set to 0.
6-4-4-19 Word 62 : Single word DMA transfer
The low order byte identifies by bit all of the Modes which are supported (e.g. if Mode 0
is supported, bit 0 is set). The high order byte contains a single bit set to indicate which
mode is active.
6-4-4-20 Word 63 : Multiword DMA transfer
The low order byte identifies by bit all the supported Modes, for example if Mode 0 is
supported, bit 0 is set. The high order byte contains a single bit set to indicate which
mode is active.
6-4-4-21 Word 64 : Flow Control PIO Transfer Modes Supported
Bits 7 through 0 of word 64 of the Identify Device Parameter information is defined as
the Advanced PIO Data Transfer Supported Field. This field is bit significant. Any
number of bits may be set in this field by the device to indicate which Advanced PIO
Modes that it is capable of supporting.
6-4-4-22 Word 65 : Minimum Multiword DMA Transfer Cycle Time Per Word
Word 65 of the parameter information of the IDENTIFY DEVICE Command is defined
as the minimum Multi-word DMA Transfer Cycle Time Per Word. This field defines, in
nanoseconds, the minimum cycle time that the device can support when performing
Multi-word DMA transfers on a per word basis.
If this field is supported, bit 1 of word 53 shall be set. Any device which supports Multi-
word DMA Mode 1 or above shall support this field, and the value in word 65 shall not
