Samsung WA31083A Technical Manual Download Page 95

Page: 95 / 95

Maintenance

2 WA31273A / WA32543A

/ WA33203A / WA32163A / WA31083A / WA32162A

There are also a number of utility programs available that you can use to back up

your data.

7-3

Service And Repair

The service and repair of the Winner 3A WA31273A / WA32543A / WA33203A /

WA32163A / WA31083A, Winner 2A WA32162A

can be done at a SAMSUNG Service

Center. Please contact your representative for warranty information and service/return
procedures

Summary of Contents for WA31083A

Page 1: ...Technical Manual 3 5 Hard Disk Drives Winner 3A 2A WA31273A WA32543A WA33203A WA31083A WA32163A WA32162A FEBRUARY 1998 REV D ...

Page 2: ... SAMSUNG ELECTRONICS CO LTD 1997 All rights reserved Requests for technical information about this product to SAMSUNG Electronics Storage System Division 94 1 IM SOO DONG KUMI CITY KYUNG BUK KOREA Trademark Acknowledgments PC AT and PC XT are registered trademarks of International Business Machines Corporation Microsoft is a U S registered trademark and MS DOS DOS and Windows are registered tradem...

Page 3: ...32162A technical manual is intended for the following readers Original Equipment Manufacturers OEMs Distributors 1 2 Manual Organization This manual provides information about installation principles of operation and interface command implementation It is organized into the following chapters Chapter 1 Scope Chapter 2 Overall Description Chapter 3 Specifications Chapter 4 Installation and Operatio...

Page 4: ... Megabits per second Mbytes s Megabytes per second MHz Megahertz mil Millinches ms Milliseconds mV Millivolts ns Nanoseconds RPM Rotations per minute TPI Tracks per inch V Volts W Watts This manual uses the following convention Computer Message Computer message refers to items you type at the computer keyboard These items are listed in all capitals in Courier New font For example FORMAT C S Comman...

Page 5: ... Reset Sector Count Register Hexadecimal Notation Hexadecimal notation is identified using the small letter form For example 30h Signal Negation A signal name is defined as active low is listed with a dash character following the signal For example RD Notes Notes are used after tables to provide you with supplementary information Host In general the system in which the drive resides is referred to...

Page 6: ...ller embedded in the disk drive PCB electronics The drive s electrical interface is compatible with the mandatory optional and vendor specific commands Drive size conforms to the industry standard 3 5 inch form factor The interface connectors are the standard 40 pin for AT Interface and 4 pin for DC power supplies High capacity is achieved by using Advanced Thin Film Inductive head and PRML Partia...

Page 7: ...nt for Green PC ATA standard PIO Mode 0 4 DMA Mode 0 2 Supports for both CHS and LBA Addressing mode Supports for all logical geometries as programmed by the host Proprietary 128K read look ahead cache with a segmented buffer and write stacking capability 1 1 interleave on read write operation Transparent media defect mapping High performance in line defective sector skipping Automatic error corre...

Page 8: ...d disk drives satisfy the following standards and regulations Underwriters Laboratory UL Standard 1950 Information technology equipment including business equipment Canadian Standards Association CSA Standard C22 2 No 3000 201 Information technology equipment including business equipment Technisher Überwachungs Verein TÜV Standard EN 60 950 Information technology equipment including business equip...

Page 9: ...DESCRIPTION WA31273A WA32543A WA33203A WA31083A WA32163A WA32162A Number of disks 1 2 3 1 2 2 Number of R W heads 2 4 5 2 4 4 Maximum recording density BPI 124 925 107 829 117 598 Maximum flux density FCI 140 541 121 308 132 298 Track density TPI 6 900 6 000 Data tracks per surface 6 740 5 963 Encoding method 8 9 GCR Interface method Fast ATA 3 E IDE Acturator type Rotary Voice Coil Servo type Emb...

Page 10: ...hes 0 8 1 01 Inner most data track radius inches 0 8413 0 8291 Outer most data track radius inches 1 7841 1 8090 Physical dimensions Length inches Width inches Height inches Weight lbs 5 75 4 00 1 00 1 2 3 3 Logical Configurations TABLE 3 3 Logical configurations DESCRIPTION WA31273A WA32543A WA33203A WA31083A WA32163A WA32162A Default logical mode Number of cylinders 2 481 4 962 6 203 2 094 4 190...

Page 11: ...0 1 rpm 4500 0 1 rpm Motor spin up time Typical 15 sec Motor spin down time Typical 7 sec Interleave 1 1 Buffer size 128 KBytes NOTES The seek time is defined as the time for the actuator to seek and settle on the desired track with the drive operating at nominal DC input voltages and nominal operating temperature The average seek time is determined by averaging the seek time for 1 000 seeks of ra...

Page 12: ...um Power Watts 5 Volts 12 Volts Spin up 564 1195 14 4 17 06 Normal Read Write 477 249 4 92 5 27 Idle 216 225 3 38 3 70 Random Seek 481 521 8 31 8 59 Standby 198 78 1 68 1 91 Sleep 120 78 1 34 1 52 NOTES Random seek means seek commands with logical random location and 30 duty cycle Random read write means a combination of random write 256 sectors commands and random read 256 sectors command ...

Page 13: ...Condensation 5 55 C 40 65 C 20 C hr Relative Humidity non condensing Operation Non operation Maximum wet bulb temperature operating non operating 8 80 8 95 29 C 40 C Altitude relative to sea level Operating Non operating 200 to 10 000 ft 1 000 to 40 000 ft Vibration 1 oct min sweep sine Operating 5 21Hz 22 400Hz Non operating 5 21Hz 22 500Hz 0 034 double amplitude 1 5 G p p 0 195 double amplitude ...

Page 14: ...163A WA31083A Winner 2A WA32162A hard disk drives can withstand levels of shock and vibration applied to any of its three mutually perpendicular axes as in the specifications for shock and vibration When packed in its shipping container the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A can withstand a drop from 90cm 5Kg Box onto a concrete surface on any of its six surf...

Page 15: ... 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A hard disk drive It also describes how to start and operate the drive 4 1 Space Requirements SAMSUNG ships the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A hard disk drives without a bezel Figure 4 1 shows the external dimensions of the drive Figure 4 1 Mechanical Dimensions ...

Page 16: ...ove it from the ESD Electro Static Discharge bag CAUTION During shipment and handling the anti static ESD bag prevents electronic component damage due to electrostatic discharge To avoid accidental damage to the drive do not use a sharp instrument to open the ESD bag 4 Save the packing material for possible future use 4 3 Mounting 1 Be sure that the system power is off 2 Mount the drive in a mount...

Page 17: ...Figure 4 2 shows the physical dimensions and mounting holes located on each side of the drive The mounting holes on the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A hard disk drive allow the drive to be mounted in any orientation Figure 4 2 Mounting Dimensions in Millimeters ...

Page 18: ...he mounting screw described in the Figure 4 3 The specified screw length allows full use of the mounting hole threads while avoiding damage or placing unwanted stress on the PCB Figure 4 3 Mounting Screw Clearance CAUTION Using mounting screws that are longer than the maximum lengths specified in Figure 4 3 voids the warranty on the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A ...

Page 19: ...ure 4 4 Table 4 1 lists the pin assignments Table 4 1 Power Connector J7 Pin Assignment PIN NUMBER POWER LINE DESIGNATION 1 12V DC 2 12V Return Ground 3 5V Return Ground 4 5V DC 4 4 2 AT Bus Interface Connector J2 The AT Bus interface connector J2 on the drive connects the drive to an adapter or an on board AT adapter in the computer J2 is a 40 pin Universal Header with two rows of 20 pins on 100 ...

Page 20: ...Installation and Operation 4 6 WA31273A WA32543A WA33203A WA32163A WA31083A WA32162A Figure 4 4 DC Power Connector J7 and AT Bus Connector J2 ...

Page 21: ...r and slave selection SLAVE Slave Mode This jumper when installed is for configuring the drive in Slave Mode Master jumper must be removed when Slave Mode is configured MASTER Master Mode This jumper when installed is for configuring the drive in Master Mode This jumper must be removed when drive is configured in Slave Mode Default Jumper Setting Master Mode Slave Jumper Setting Slave Mode ST SST ...

Page 22: ...ster and slave jumpers To configure a drive as the Master Drive 0 install a jumper on the master pins Samsung ships the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A hard disk drives from the factory with the master jumper installed Drive 0 and slave Jumper opened To specify a drive as the Slave Drive remove the master jumper and install the jumper on the slave pins NOT...

Page 23: ...Installation and Operation WA31273A WA32543A WA33203A WA32163A WA31083A WA32162A 4 9 Figure 4 5 Jumper Pin Locations on the Drive PCB ...

Page 24: ... using a 40 pin ribbon cable Ensure that pin 1 of the drive is connected to pin 1 of the motherboard connector To install the drive in a system without a 40 pin AT bus connector on its mother board you need an AT bus adapter kit The kit includes an adapter and a ribbon cable which is used to connect the board to the drive NOTE Removing pin 20 of the drive ensures the connector cannot be installed ...

Page 25: ...ram refer to the system manual for your PC 3 Enter the appropriate parameters for the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A During the AT system CMOS setup you must enter the drive type for Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A the hard disk drives This procedure allows the system to recognize the drive by translating its phys...

Page 26: ... of this manual 4 Save the set up parameters and re boot the system using the operating system installation disk for example MS DOS then follow the installation instructions in your operating system manual If you are using MS DOS 1 Run the FDISK utility or a third party partitioning program NOTE When using DOS version 3 2 or below the DOS partitions only 32 Mbytes of the drive s capacity DOS 3 3 p...

Page 27: ...tor latch assembly and base casting which includes the DC motor assembly HDA assembly is done in a Class 100 clean room These subassemblies cannot be adjusted or field repaired CAUTION To avoid contamination in the HDA never remove or adjust its cover and seals Disassembling the HDA voids your warranty The Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A products are part ...

Page 28: ...r spindle bearing assembly disk mounting hub and a labyrinth mechanical seal The entire spindle motor assembly is completely enclosed in the HDA and screwed to the base casting The labyrinth seal prevents bearing lubricant from coming out into the HDA The motor rotates the spindle shaft at 5400 Winner 3A rpm and 4500 Winner 2A rpm Figure 5 1 Exploded Mechanical view ...

Page 29: ... arms of the actuator The flexible circuit connects the read write heads with the PCBA via a connector through the base casting The flexible circuit contains a read write Preamplifier IC 5 1 6 Rotary Positioning Assembly The rotary positioner or rotary voice coil motor is a SAMSUNG proprietary design that consists of upper and lower permanent magnetic yokes fixed to the base casting and a rotary o...

Page 30: ... 2 shows a simplified block diagram of the the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A electronics The components are mounted only on one side of the PCBA The Preamplifier and Write Driver IC is the only electrical component that is not on the PCBA It is mounted on the flexible circuit inside the HDA Locating the Preamplifier IC as close as possible to the read wr...

Page 31: ...owing features 40ns cycle time at 5 Volts 16 bit Fixed Point DSP PINE Core 16 x 16bit 2 s Complement Parallel Multiplier with 32bit Product Single Cycle Multiply and Accumulate 36bit ALU with Two 36bit Accumulators Programmable DPLL for DSP clock On chip Data RAM 256 word x 2 On chip Program RAM 3K word Other Features 5V 10 Operation Programmable Power down Modes CMOS 0 65µm Standard cell technolo...

Page 32: ...t read write commands either completely automatically without any microprocessor intervention semi automatically with minimal microprocessor intervention or manually with the aid of the microprocessor Of particular interest to most designers are the significant advances in ATA automation which have been incorporated into the SID 9501D The highlights of ATA automation are Automatic data transfer ma...

Page 33: ...pe transfers includes single word multi word and synchronous DMA transfers DMA transfers and PIO transfers utilize the bus in 8 or 16 bit mode depending upon the command being executed The bus is automatically switched between 16 and 8 bit mode while performing Read Long and Write Long commands at the time of ECC byte transfers Additional functionality is provided in the Host Interface block by th...

Page 34: ...path in ATA mode A parity bit is available for each of the low and high order eight bits EDO DRAM support is provided with up to 4 MB addressing capability Page 8 mode with up to 50 MB buffer bandwidth The buffer Control block incorporates very flexible segmentation support Two operational segments can be set up to support general read write auto write and read caching Auto Read algorithms The seg...

Page 35: ...kipping servo burst data splitting branching on critical buffer status address verification and data compare operations Once the Disk Sequencer is started it executes each word in logical order At the completion of the current instruction word it either continues to the next instruction continues to execute some other instruction based upon an internal or external condition having been met or stop...

Page 36: ...w for greater data integrity in a headerless environment Error detection and correction is handled in the Disk Control block Automatic on the fly hardware correction will take place for up to three symbols in error per interleave Correction is guaranteed to complete before the ECC Field of the sector following the sector where the error occurred utilizing standard ATA size sectors Optional burst l...

Page 37: ... Controller When it is connected to the output of the head amplifier it performs the signal conditioning data qualification data synchronization and encoding decoding task with a minimum of external components There are 5 major functional modules in the Read Write IC Automatic Gain Control AGC Filter Equalizer Pulse Qualifier Data Separator Servo Demodulator These modules are described in the foll...

Page 38: ...he qualified servo pulse and the polarity of the pulse During data reads this qualifier is used for ensuring pulse polarity changes during VCO sync field counting The viterbi qualifier is only used during data read mode after the sync field count has been achieved This qualifier has two significant blocks one that feeds the other The first block is the sampled pulse detector it performs the pulse ...

Page 39: ... Sector Servo System Positioning information is radially located in 72 evenly spaced servo sectors on each track Radial position information can be provided from these sectors for each data head 72 times per revolution Because the drive used multiple data zones and each zone has a different bit density split data fields are necessary to optimally use the non servo area of the disk The servo area r...

Page 40: ...e Sequencer module identifies the data as belonging to the target sector After a full sector is read the SID 9501D checks to see if the firmware needs to apply an ECC algorithm to the data The buffer Controller section of the SID 9501D stores the data in the cache and transmits the data to the AT bus 5 4 2 The Write Channel The signal path for the write channel follows the reverse order of that fo...

Page 41: ... the cache because more than 50 percent of all disk requests are sequential It takes microseconds rather than milliseconds to retrieve this cached data Thus Read Caching can provide substantial performance improvements during at least half of all disk requests For example Read Caching could save most of the disk transaction time by eliminating the seek and rotational latency delays that prominentl...

Page 42: ...rent command Read commands work similarly The previous write is allowed to finish before the read operation starts If a defective sector is found during a write that sector is automatically relocated before the write occurs This ensures that cached data that already has been reported as written successfully gets written even if an error should occur If the sector is not automatically relocated the...

Page 43: ... overhead Capability to reassign not only write errors but also read errors available Use more scratch pad to save variables during auto reassignment to minimize use of internal memory Basic Operation Use all unused spare sectors of each zone for reassign Reserve track of each spare cylinder for auto reassign Reassign List Table is initialized at the end of defect free process in factory test proc...

Page 44: ... 5 6 SMART The Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A supports SMART Self Monitoring Analysis and Reporting Technology The following commands are featured SAAS Disable Enable 0 1 Attribute Auto Save SDSO Disable SMART operation SESO Enable SMART operation SISV Initialize SMART variables SRAT Read Attribute values SRSS Return SMART status SSAV Save Attribute Value...

Page 45: ... either a high more positive voltage or low less positive voltage state A dash character at the beginning or end of a signal name indicates that it is asserted at the low level active low No dash or a plus character at the beginning or end of a signal name indicates it is asserted high active high An asserted signal may be driven high or low by an active circuit or it may be allowed to be pulled t...

Page 46: ...to select the Control Block Registers 6 2 3 3 DA0 2 Drive Address Bus This is the 3 bit binary coded address asserted by the host to access a register or data port in the drive 6 2 3 4 DASP Drive Active Slave Present This is a time multiplexed signal that indicates that a drive is active or that Drive 1 is present This signal is an open collector output and each drive has a 10K ohm pull up resisto...

Page 47: ...CK i e the drive shall wait until the host asserts DMACK before negating DMARQ and re asserting DMARQ if there is more data to transfer When a DMA operation is enabled IOCS16 CSIFX shall not be asserted and transfers shall be 16 bits wide 6 2 3 10 INTRQ Drive Interrupt This signal is used to interrupt the host system INTRQ is asserted only when the drive has a pending interrupt the drive is select...

Page 48: ...e Following a power on reset software reset or RESET Drive 1 negates PDIAG within 1 msec to indicate to Drive 0 that it is busy Drive 1 then asserts PDIAG within 30 seconds to indicate that it is no longer busy and is able to provide status After the assertion of PDIAG Drive 1 will be unable to accept commands until it has finished its reset procedure and is Ready DRDY 1 Following the receipt of a...

Page 49: ...ome event requires that the drive s be reset following power on Table 6 1 shows the correlation between the signals at the ATA interface and the host AT bus Table 6 1 AT Bus Interface Signals Drive Connector Direction AT System BUS Signal Name Pin No RESET 1 RESET DRV Ground 2 Ground DB7 3 SD7 DB8 4 SD8 DB6 5 SD6 DB9 6 SD9 DB5 7 SD5 DB10 8 SD10 DB4 9 SD4 DB11 10 SD11 DB3 11 SD3 DB12 12 SD12 DB2 13...

Page 50: ... DMARQ 21 DMARQ Ground 22 Ground IOW 23 IOW Ground 23 Ground IOR 25 IOR Ground 26 Ground IORDY 27 IORDY Reserved 28 No Connection DMACK 29 DMACK Ground 30 Ground INTRQ 31 INTRQ IOCS16 32 IOCS16 ADDR1 33 SA1 PDIAG 34 PDIAG ADDR0 35 SA0 ADDR2 CS1FX 36 37 SA2 CS0 CS3FX 38 CS1 DASP 39 DASP Ground 40 Ground Drive Intercommunication Signals Drive 1 Drive 0 Host 34 PDIAG 34 34 34 39 DASP 39 39 39 ...

Page 51: ... I Drive chip Select 0 CS3FX 38 I Drive chip Select 1 DA0 35 I Drive Address Bus Bit 0 DA1 33 I Bit 1 DA2 36 I Bit 2 DASP 39 I O Drive Active Slave Present DD0 17 I O Drive Data Bus Bit 0 DD1 15 I O Bit 1 DD2 13 I O Bit 2 DD3 11 I O Bit 3 DD4 9 I O Bit 4 DD5 7 I O Bit 5 DD6 5 I O Bit 6 DD7 3 I O Bit 7 DD8 4 I O Bit 8 DD9 6 I O Bit 9 DD10 8 I O Bit 10 DD11 10 I O Bit 11 DD12 12 I O Bit 12 DD13 14 I...

Page 52: ... O Drive Interrupt IOCS16 32 O Drive 16 bit I O IORDY 27 O I O Channel Ready PDIAG 34 I O Passed Diagnostics RESET 1 I Drive Reset Keypin 20 Pin used for keying the interface connector NOTE A minus sign follows the name of any signal that is asserted as active low Direction DIR is in reference to the drive IN indicates input to the drive OUT indicates output from the drive I O indicates that the s...

Page 53: ... command completion When two devices are daisy chained on the interface commands are written in parallel to both devices this is true for all except the Execute Diagnostics command only the selected device executes the command On an Execute Diagnostics command addressed to Device 0 both devices shall execute the command and Device 1 shall post its status to Device 0 via PDIAG Drives are selected b...

Page 54: ...r 0 Irrespective of translate mode geometry set by the host the LBA address of a given sector does not change LBA cylinder heads_per_cylinder heads sectors_per_track sector 1 6 3 2 I O Register Address Communication to or from the drive is through an I O Register that routes the input or output data to or from registers addressed by a code on signals from the host CS1FX CS3FX DA2 DA1 DA0 DIOR and ...

Page 55: ...16 23 LBA bits 16 23 A N 1 1 0 Drive Head Drive Head A N 1 1 0 LBA bits 24 27 LBA bits 24 27 A N 1 1 1 Status Command N N X X X Invalid Address Invalid Address Mapping of registers in LBA mode Logic conventions are A signal asserted N signal negated X don t care 6 3 3 Control Block Register Descriptions 6 3 3 1 Alternate Status Register 3F6h This register contains the same information as the Statu...

Page 56: ...bit for drive 0 When drive 0 is selected and active nDS0 0 NOTE Caching translation and master slave may cause this register to contain invalid data 6 3 3 3 Device Control Register 3F6h The bits in this register are as follows 7 6 5 4 3 2 1 0 X X X X 1 SRST nIEN 0 SRST is the host software reset bit The drive is held reset when this bit is set If two disk drives are daisy chained on the interface ...

Page 57: ... the completion of any command except Execute Drive Diagnostic the contents of this register are valid when ERR 1 in the Status Register Following a power on a reset or completion of an Execute Drive Diagnostic command this register contains a Diagnostic Code see Table 6 5 7 6 5 4 3 2 1 0 BBK UNC 0 IDNF 0 ABRT TK0NF AMNF BBK Bad Block Detected indicates a bad block mark was detected in the request...

Page 58: ...of the command this register is updated to reflect the current disk address The most significant bits of the cylinder address are loaded into the Cylinder High Register 6 3 4 7 Cylinder Low Register 1F4h In CHS mode this register contains the low order 8 bits of the starting cylinder address for any disk access In LBA mode this register contains bits 16 23 of the LBA At the end of the command this...

Page 59: ...he drive is Not Ready 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR BSY Busy is set whenever the drive has access to the Command Block Registers The host should not access the Command Block Register when BSY 1 When BSY 1 a read of any Command Block Register returns the contents of the Status Register This bit is set by the drive under the following circumstances a within 400 nsec after the neg...

Page 60: ... again indicates the current Seek Complete status DRQ Data Request indicates that the drive is ready to transfer a word or byte of data between the host and the drive CORR Corrected Data indicates that a correctable data error was encountered and the data has been corrected This condition does not terminate a data transfer IDX Index is set once per disk revolution ERR Error indicates that an error...

Page 61: ...pon receipt of a Class 3 command the drive sets BSY within 400 nsec sets up the sector buffer for a write operation sets DRQ within 20 msec and clears BSY within 400 nsec of setting DRQ NOTE DRQ may be set so quickly on Class 2 and Class 3 that the BSY transition is too short for BSY 1 to be recognized If a new command is issued to a drive which has an uncompleted command subsequently referred to ...

Page 62: ...h y D 1 Set Multiple Mode C6h y D 1 Sleep Mode 99h E6h D 1 Standby 96h E2h y D 1 Standby Immediate 94h E0h D 2 Write Buffer E8h D 3 Write DMA w retry CAh y y y y 3 Write DMA w o retry CBh y y y y 3 Write Multiple C5h y y y y 2 Write Sector s w retry 30h y y y y 2 Write Sector s w o retry 31h y y y y 2 Write Long w retry 32h y y y y 2 Write Long w o retry 33h y y y y 3 SMART Commands 0B0h CY Cylind...

Page 63: ...ives if present shall execute this command If Drive 1 is present Drive 1 asserts PDIAG within 5 seconds Drive 0 waits up to 6 seconds for Drive 1 to assert PDIAG If Drive 1 has not asserted PDIAG indicating a failure Drive 0 appends 80h to its own diagnostic status Both drives execute diagnostics If Drive 1 diagnostic failure is detected when Drive 0 status is read Drive 1 status is obtained by se...

Page 64: ...e device sets BSY bit prepares to transfer the 256 words of device identification data to the host sets the DRQ bit clears the BSY bit and generates an interrupt The host cab then transfer the data by reading the Data register The parameter words in the buffer have the arrangement and meanings defined in Table 6 6 All reserved bits or words shall be zero The F V column indicates if the word or par...

Page 65: ...r of user addressable logical cylinders in the default translation mode 6 4 4 2 Word 3 Number of logical heads The number of user addressable logical heads in the default translation mode 6 4 4 3 Word 6 Number of logical sectors per logical track The number of user addressable sectors per logical track in the default translation mode 6 4 4 4 Word 10 19 Serial Number If word 10 of this field is 000...

Page 66: ...port Bits 7 0 of this word define the maximum number of sectors per block that the device supports for READ WRITE MULTIPLE commands If a device supports the READ WRITE MULTIPLE and SET MULTIPLE MODE commands these bits contain a non zero value If the device does not support the READ WRITE MULTIPLE and SET MULTIPLE MODE commands these bits shall be zero 6 4 4 9 Word 49 Capabilities 6 4 4 9 1 Standb...

Page 67: ...MA data transfer cycle timing mode The DMA transfer timing for each ATA device falls into categories which have unique parametric timing specifications To determine the proper device timing category compare the Cycle Time specified in figure 11 with the contents of this field The value returned in Bits 15 8 should fall into one of the categories specified in figure 11 i e 0 1 or 2 and if it does n...

Page 68: ...bit all of the Modes which are supported e g if Mode 0 is supported bit 0 is set The high order byte contains a single bit set to indicate which mode is active 6 4 4 20 Word 63 Multiword DMA transfer The low order byte identifies by bit all the supported Modes for example if Mode 0 is supported bit 0 is set The high order byte contains a single bit set to indicate which mode is active 6 4 4 21 Wor...

Page 69: ... this field and the value in word 66 shall not be less than the value in word 65 6 4 4 24 Word 67 Minimum PIO Transfer Cycle Time Without Flow Control Word 67 of the parameter information of the IDENTIFY DEVICE Command is defined as the Minimum PIO Transfer without Flow Control Cycle Time This field defines in nanoseconds the minimum cycle time that if used by the host the device guarantees data i...

Page 70: ...r specific obsolete 8 vendor specific obsolete 7 1 removable media device 6 1 not removable controller and or device 5 vendor specific obsolete 4 vendor specific obsolete 3 vendor specific obsolete 2 vendor specific obsolete 1 vendor specific obsolete 0 Reserved 1 Number of logical cylinders 2 Reserved 3 Number of logical heads 4 Vendor specific obsolete 5 Vendor specific obsolete 6 Number of logi...

Page 71: ...rved 13 1 Standby time values as specified in this standard are supported 0 Standby timer values are vendor specific 12 Reserved for advanced PIO mode support 11 1 IORDY supported 0 IORDY may be supported 10 1 IORDY can be disabled 9 1 LBA supported 8 1 DMA supported 7 0 Vendor specific 50 Reserved 51 15 8 PIO data transfer cycle timing mode 7 0 Vendor specific 52 15 8 DMA data transfer cycle timi...

Page 72: ...ode only 62 15 8 Single word DMA transfer mode active 7 0 Single word DMA transfer modes supported 63 15 8 Multiword DMA transfer mode active 7 0 Multiword DMA transfer modes supported 64 15 8 Reserved 7 0 Advanced PIO transfer modes supported 65 Minimum Multiword DMA xfer cycle time per Word 15 0 Cycle time in nanoseconds 66 Mfg s recommended Multiword DMA xfer cycle time 15 0 Cycle time in nanos...

Page 73: ... Count Register Contents Corresponding Time out Period 0 00h Timeout Disabled 1 240 01h FOh value 5 seconds 241 251 F1h FBh value 240 30 minutes 252 FCh 21 minutes 253 FDh 8 hours 254 FEh Reserved 255 FFh 21 minutes 15 seconds 6 4 6 Idle Immediate 95h E1h This command causes the drive to set BSY enter the Idle Mode clear BSY and generate an interrupt The interrupt is generated even though the driv...

Page 74: ... be synchronized so that sequential Write Buffer E8h and Read Buffer commands access the same 512 bytes within the buffer 6 4 11 Read DMA C8h This command executes in a similar manner to the Read Sector s command except for the following the host initializes a slave DMA channel prior to issuing the command data transfers are qualified by DMARQ and are performed by the slave DMA channel the drive i...

Page 75: ...by a final partial block transfer The partial block transfer shall be for n sectors where n Remainder Sector Count Block Count If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled the Read Multiple operation is rejected with an Aborted Command error Disk errors encountered during Read Multiple commands are post...

Page 76: ...flawed data is pending in the sector buffer 6 4 15 Read Verify Sector s 40h This command is identical to the Read Sectors command except that DRQ is never set and no data is transferred to the host See 6 6 3 for protocol When the command is accepted the drive sets BSY When the requested sectors have been verified the drive clears BSY and generates an interrupt Upon command completion the Command B...

Page 77: ...ands When the drive receives this command it sets BSY checks the contents of the Feature register clears BSY and generates an interrupt If the value in the Feature Register is not supported or is invalid the drive posts an Aborted Command error Refer to section 6 6 3 for protocol A host can choose the transfer mechanism by Set Transfer Mode and specifying a value in the Sector Count Register The u...

Page 78: ... stopped BSY is cleared an interrupt is generated and the interface becomes inactive The only way to recover from Sleep mode without a reset or power on is for the host to issue a software reset A drive shall not power on in Sleep Mode nor remain in Sleep Mode following a reset sequence If the drive is already spun down the spin down sequence is not executed 6 4 20 Standby 96h E2h This command cau...

Page 79: ... Mode command which shall be executed prior to the Read Multiple command When the Write Multiple command is issued the Sector Count Register contains the number of sectors not the number of blocks or the block count requested If the number of requested sectors is not evenly divisible by the block count as many full blocks as possible are transferred followed by a final partial block transfer The p...

Page 80: ...rite Sector s 30h This command writes from 1 to 256 sectors as specified in the Sector Count Register a sector count of zero requests 256 sectors beginning at the specified sector Refer to Section 6 7 for the DRQ IRQ and BSY protocol on data transfers If the drive is not already on the desired track an implied seek is performed Once at the desired track the drive searches for the appropriate ID fi...

Page 81: ... reset is accepted and with BSY set a Both drives perform hardware initialization b Both drives clear any previously programmed drive parameters c Both drives may revert to the default condition d Both drives load the Command Block Registers with their default values e If a hardware reset Drive 0 waits for DASP to be asserted by Drive 1 f If operational Drive 1 asserts DASP g Drive 0 waits for PDI...

Page 82: ...ic Code see Table 6 5 Following any reset the host should issue an Initialize Drive Parameters command to ensure the drive is initialized as desired 6 5 2 Error Posting The errors that are valid for each command are defined in Table 6 7 See 6 3 4 4 and 6 3 4 10 for the definition of the Error Register and Status Register bits ...

Page 83: ...V V V V V Idle Immediate V V V V V Initialize Drive Parms V V V NOP V Recalibrate V V V V V V Read Buffer V V V V V Read DMA V V V V V V V V V V Read Long V V V V V V V V Read Multiple V V V V V V V V V V Read Sector s V V V V V V V V V V Read Verify Sector s V V V V V V V V V V Seek V V V V V V Set Features V V V V V Set Multiple Mode V V V V V Sleep V V V V V Standby V V V V V Standby Immediate ...

Page 84: ...SC Disk seek complete not detected ABRT Abort command error CORR Corrected data error TK0NF Track zero not found error ERR Error bit in the Status Register 6 5 3 Power Conditions Winner 3A reduces the power required to operate as shown in Table 6 10 which describes operating mode and the status of major components Table 6 10 Power Saving Mode MODE R W Spindle VCM Interface SLEEP OFF OFF OFF Disk O...

Page 85: ...matically transitions to the Standby Mode upon expiration of a prescribed 1 minute spin down counter In the Idle mode the drive is capable of responding immediately to media access requests A drive in Idle mode may take longer to complete the execution of a command than in Normal mode because it may have to activate ENDEC and R W circuit 6 5 3 4 Normal mode In Normal mode the drive is capable of r...

Page 86: ...d Long 22h Read Sector s 20h Read Multiple C4h Execution includes the transfer of one or more 512 byte 512 bytes on Read Long sectors of data from the drive to the host a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the command code to the Command Register c The drive sets BSY and prepares for data transfer d...

Page 87: ...nd a b e Setup Issue Read Command Status BSY 0 BSY 1 BSY 0 DRDY 1 DRQ 1 DRQ 0 Assert Negate INTRQ INTRQ Although DRQ 1 there is no data to be transferred under this condition 6 6 2 PIO Data Out Commands This class includes Format 50h Write Buffer E8h Write Long 32h Write Multiple C5h Write Sector s 30h Execution includes the transfer of one or more 512 byte 512 bytes on Write Long sectors of data ...

Page 88: ... DRQ g After detecting INTRQ the host reads the Status Registers h The drive clears the interrupt i If transfer of another sector is required the above sequence is repeated from d 6 6 2 1 PIO Write Command a b e e Setup Issue Transfer Read Transfer Read Command Data Status Data Status BSY 0 BSY 1 BSY 0 BSY 1 BSY 0 BSY 1 BSY 0 DRDY 1 DRQ 1 DRQ 0 DRQ 1 DRQ 0 Assert Negate Assert Negate INTRQ INTRQ I...

Page 89: ...rate 1Xh Seek 7Xh Set Features EFh Set Multiple Mode C6h Sleep 99h E6h Standby 96h E2h Standby Immediate 94h E0h Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the command code to the Command Register c The drive sets BSY d When the drive has completed pro...

Page 90: ...handler for DMA transfers is different in that no intermediate sector interrupts are issued on multi sector commands the host resets the DMA channel prior to reading status from the drive The DMA protocol allows high performance multi tasking operating system to eliminate processor overhead associated with PIO transfers a Command phase 1 Host initializes the slave DMA channel 2 Host updates the Co...

Page 91: ...nitialize DMA Command DMA data transfer Reset DMA Status BSY 0 BSY 1 BSY x DRQ x BSY 1 nIEN 0 BSY 0 6 6 5 2 Aborted DMA transfer Initialize DMA Command DMA data Reset DMA Status BSY 0 BSY 1 BSY x DRQ 1 BSY 1 nIEN 0 BSY 0 6 6 5 3 Aborted DMA Command Initialize DMA Command Reset DMA Status BSY 0 BSY 1 BSY 1 BSY 0 nIEN 0 ...

Page 92: ...0 ns TADS Address setup time to DIORB DIOWB 5 ns TADH Address hold time from DIORB DIOWB 10 ns TIOCSL Address setup time to IOCS16B 15 ns TIOCHL DIORB DIOWB asserted to IORDY 20 ns TIOCHPW IORDY pulse width 25 ns TIOCSH Address hold time from IOCS16B 14 ns THCS CS setup time from IOCS16B 10 ns THCH CS hold time from DIORB DIOWB 10 ns TDDRQL DIORB DIOWB asserted to DMARQ 40 ns TDACKS DMACKB setup t...

Page 93: ...A WA32162A 6 49 6 7 2 ATA PIO Timing ATA PIO Timing is shown in Figure 6 2 ATA PIOTiming CS1FXB CS3FXB DIORB DIOWB DA DD READ READ DATA DD WRITE WRITE DATA IORDY IOCS16B TIOCSL TI OCHL TI OCHPW TWDS TWDH TADV TRDH TRDA TRDS TPW THCH TADH THCS TIOCSH Figure 6 2 ATA PIO Timing ...

Page 94: ...the media 2 Do not lift the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A by the PCB 3 Avoid harsh shocks or vibrations to the drive at all times 4 Avoid static discharge when handling the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A 5 Do not touch the components on the PCB 6 Observe the environmental limits specified for this product as lis...

Page 95: ...grams available that you can use to back up your data 7 3 Service And Repair The service and repair of the Winner 3A WA31273A WA32543A WA33203A WA32163A WA31083A Winner 2A WA32162A can be done at a SAMSUNG Service Center Please contact your representative for warranty information and service return procedures ...

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Samsung WA31083A, Technical Manual

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