AT INTERFACE and ATA COMMANDS
6-
48 WA31273A / WA32543A / WA33203A / WA3216A / WA31083A / WA32162A
6-7
Timing
6-7-1 ATA Host Interface Timing Parameters
ATA Host Interface Timing parameters are shown in Table 6-12.
Table 6-12.
ATA Host Interface Timing Parameters
Symbol
PARAMETER
TIMING
UNIT
MIN
TYP
MAX
TPW
DIORB/DIOWB- Pulse Width
10
ns
TRDA
DD Drive from DIORB asserted
25
ns
TWDS
Write data setup time to DIOWB
5
ns
TWDH
Write data hold time from DIOWB
5
ns
TRDH
Read data hold time from DIORB
20
70
ns
TADS
Address setup time to DIORB/ DIOWB
5
ns
TADH
Address hold time from DIORB/DIOWB
10
ns
TIOCSL
Address setup time to IOCS16B
15
ns
TIOCHL
DIORB/DIOWB asserted to IORDY
20
ns
TIOCHPW
IORDY- pulse width
25
ns
TIOCSH
Address hold time from IOCS16B
14
ns
THCS
CS setup time from IOCS16B
10
ns
THCH
CS hold time from DIORB/DIOWB
10
ns
TDDRQL
DIORB/DIOWB asserted to DMARQ
40
ns
TDACKS
DMACKB setup time to DIORB/DIOWB
0
ns
TDKA
DMACKB asserted to DD valid
28
ns
TADV
CS and DA valid to DD valid
25
ns
TMACH
DIORB/DIOWB hold time to DMACKB
5
ns
TDHT *
DMACKB negated to DD tristated
ns
TMWC
Multi-word DMA cycle time
120
ns
*
Applies at end of an ATA multi-word DMA cycle, when DMACKB is negated
