S5PV210_HARDWARE DESING GUIDE REV 1.0
85
5.
MEMORY SUBSYSTEM
5.1. Signal Description
Signal
I/O
Description
XDDR2SEL
I
Memory Type Selection (0; LPDDR1, 1: DDR2, LPDDR2)
Xm1SCLK, Xm2SCLK
O
Memory Clock
Xm1nSCLK, Xm2nSCLK
O
Memory Negative Clock
Xm1RASn, Xm2RASn
O
Row Address Selection
Xm1CASn, Xm2CASn
O
Column Address Selection
Xm1WEn, Xm2WEn
O
Write Enable
Xm1DATA[31:0], Xm2DATA[31:0]
I/O
Memory Data Bus
Xm1DQM[3:0], Xm2DQM[3:0]
O
Write Masking Per Byte
Xm1DQS[3:0], Xm2DQS[3:0]
I/O
Data Strobe Signal Per Byte
Xm1DQSn[3:0], Xm2DQSn[3:0]
I/O
Data Strobe Negative Signal Per Byte
ADCT[18:0](Address & Control),
CKE
O
Memory Address, Bank Address, CS, CKE signals
5.2. TQ : Temperature Indicator
Samsung mDDR includes the enhanced feature, Temperature Indicator (TQ), which informs MDRAM’s internal
temperature of controller, in order to notice that DRAM inside temperature become higher than 85’C which is the
highest temperature guaranteed normally in the specification. In over 85’C, DRAM refresh cycle is derated according
as the temperature goes up, controllers need to adjust auto-refresh cycle based on MDRAM temperature. Generally, it
is well known that the auto-refresh cycle of DRAM tends to be half every 10’C up over 85’C. The guidance for auto-
refresh cycle over 85’C is provided
by
specification.
Temp Auto-Refresh
cycle
-25 ~ 85C
7.8us
85 ~ 95 C
3.9us
5.3. PCB LAYOUT GUIDELINES FOR MEMORY
TQ
Mobile
DRAM
S5PV2
10
CMD
Block diagram for TQ
