S5PV210_HARDWARE DESING GUIDE REV 1.0
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6. SROM Controller
6.1. Signal Description
Signal
I/O
Description
SROM_CSn[5:0]
O
SROM Chip select
Note) Bank0 supports only 16bit data bus width.
EBI_OEn
O
Memory Port 0 SROM / OneNAND Output Enable
EBI_WEn
O
Memory Port 0 SROM / OneNAND Write Enable
EBI_BEn[1:0]
O
Memory Port 0 SROM Byte Enable
SROM_WAITn
I
Memory Port 0 SROM nWait
EBI_DATA_RDn
O
Memory Port 0 SROM/OneNAND/CF
If data is output, this signal goes to High.
If data is input, this signal goes to Low.
EBI_ADDR[15:0]
O
Memory port 0 Address bus
EBI_DATA[15:0]
IO
Memory port 0 Data bus
SRAM/ROM
S5PV210
8bit data bus
A0
Xm0ADDR0
Half-word base(AddrMode =0)(default)
A0
Xm0ADDR0
Addr.
connection
16bit data
bus
Byte base(AddrMode =1)
A0
Xm0ADDR1
Note.
1) SROM_BW [AddrMode] : Register for Address base of each memory bank
2) Bank0 supports only 16bit data bus width.
