Samsung S5PV210 Hardware Design Manual Download Page 128 | Manualshive

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S5PV210_HARDWARE DESING GUIDE REV 1.0

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25. IIS BUS CONTROLLER

25.1. Signal Description

Signal

I/O

Description

I2S_1_SCLK

IO

IIS-bus serial clock for channel 1

I2S_1_CDCLK

IO

IIS CODEC system clock for channel 1

I2S_1_LRCK

IO

IIS-bus channel select clock for channel 1

I2S_1_SDI

I

IIS-bus serial data input for channel 1

I2S_1_SDO

O

IIS-bus serial data output for channel 1

I2S_2_SCLK

IO

IIS-bus serial clock for channel 2

I2S_2_CDCLK

IO

IIS CODEC system clock for channel 2

I2S_2_LRCK

IO

IIS-bus channel select clock for channel 2

I2S_2_SDI

I

IIS-bus serial data input for channel 2

I2S_2_SDO

O

IIS-bus serial data output for channel 2

25.2. External Clock Source

S5PV210 provides a master clock to the codec through the Xi2sCDCLK line. This configuration has an advantage
that it is not necessary to configure oscillator circuit. For the making Master Clock, S5PV210 uses and divides
EPLL, MPLL or PCLK (refer to the User’s Manual). If an oscillator circuit is configured for a precise clock for the
Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as a source of
master clock through the Xi2sCDCLK line.

S5PV210 can supply 24MHz clock to Codec chip via CLKOUT line.(refer to the User’s Manual). Even at Power
down mode, this signal keep supplying to Codec chip. When Codec chip need 24MHz, external oscillator circuit can
be reduced by using this configuration.

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Summary of Contents for S5PV210

Page 1: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 Hardware Design Guide S5PV210 RISC Microprocessor FEB 8 2010 REV 1 0 ...

Page 2: ... disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgic...

Page 3: ...roduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 TEL 82 031 209 4356 FAX 82 031 209 3262 Home Page http www samsungsemi com Printed in the Republic of Kor...

Page 4: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 4 Revision History Revision No Description of Change Refer to Author s Date 1 0 First release version Feb 08 2010 ...

Page 5: ...9 4 2 Booting Option 81 4 3 Feature of the IROM Boot mode 82 4 4 Clock 83 5 MEMORY SUBSYSTEM 85 5 1 Signal Description 85 5 2 TQ Temperature Indicator 85 5 3 PCB LAYOUT GUIDELINES FOR MEMORY 85 6 SROM CONTROLLER 88 6 1 Signal Description 88 6 2 SRAM ROM Interface Examples 89 7 ONENAND CONTROLLER 90 7 1 Signal Description 90 7 2 Circuit Diagram Example 91 8 NAND FLASH CONTROLLER 92 8 1 Signal Descr...

Page 6: ...main 102 14 3 Circuit Diagram Example 102 14 4 USB SIGNAL ROUTING 103 15 USB 2 0 HS OTG 105 15 1 Signal Descriptoin 105 15 2 Power Domain 105 16 MODEM INTERFACE 107 16 1 Signal Description 107 16 2 Pin Connection Example 107 17 SD MMC HOST CONTROLLER 109 17 1 Signal Description 109 17 2 Muxed Signal usage 109 18 TSI 111 18 1 Signal Description 111 18 2 Connection Example 111 19 DISPLAY CONTROLLER ...

Page 7: ...LTI AUDIO INTERFACE V5 1 126 24 1 Signal Description 126 24 2 Audio Port 126 25 IIS BUS CONTROLLER 128 25 1 Signal Description 128 25 2 External Clock Source 128 25 3 Connection Example 129 26 AC97 CONTROLLER 130 26 1 AC97 Signal Description 130 26 2 Audio Ports 130 26 3 Connection Example 130 27 PCM BUS CONTROLLER 131 27 1 Signal Description 131 27 2 External Clock Source 132 27 3 Connection Exam...

Page 8: ...tion function in only sleep mode and released by setting Enable_GPIO bit others 31 Ret_CF this signal has a retention function in power down mode and released by setting Enable_CF_IO bit others 30 Ret_MMC this signal has a retention function in power down mode and released by setting Enable_ MMC_IO bit others 29 Ret_UART this signal has a retention function in power down mode and released by setti...

Page 9: ...L UART_0_TXD G E Ret_IO NC XuCTSn 0 GPA0 2 GPI PD I L UART_0_CTSn G E Ret_IO NC XuRTSn 0 GPA0 3 GPI PD I L UART_0_RTSn G E Ret_IO NC XuRXD 1 GPA0 4 GPI PD I L UART_1_RXD G E Ret_IO NC XuTXD 1 GPA0 5 GPI PD I L UART_1_TXD G E Ret_IO NC XuCTSn 1 GPA0 6 GPI PD I L UART_1_CTSn G E Ret_IO NC VDD_EXT0 XuRTSn 1 GPA0 7 GPI PD I L UART_1_RTSn G E Ret_IO NC VDD_EXT1 XuRXD 2 GPA1 0 GPI PD I L UART_2_RXD UART...

Page 10: ...UA RT NC for RP Low Power Audio debugging XuRXD 3 GPA1 2 GPI PD I L UART_3_RXD UART_2_CTSn G E Ret_UA RT NC XuTXD 3 GPA1 3 GPI PD I L UART_3_TXD UART_2_RTSn G E Ret_UA RT NC XspiCLK 0 GPB 0 GPI PD I L SPI_0_CLK G E Ret_IO NC XspiCSn 0 GPB 1 GPI PD I L SPI_0_nSS G E Ret_IO NC XspiMISO 0 GPB 2 GPI PD I L SPI_0_MISO G E Ret_IO NC VDD_EXT0 XspiMOSI 0 GPB 3 GPI PD I L SPI_0_MOSI G E Ret_IO NC VDD_EXT2 ...

Page 11: ...O NC Xi2s1SCLK GPC0 0 GPI PD I L I2S_1_SCLK PCM_1_SCLK AC97BITCLK G E Ret_IO NC Xi2s1CDCL K GPC0 1 GPI PD I L I2S_1_CDCLK PCM_1_EXTCLK AC97RESETn G E Ret_IO NC Xi2s1LRCK GPC0 2 GPI PD I L I2S_1_LRCK PCM_1_FSYNC AC97SYNC G E Ret_IO NC Xi2s1SDI GPC0 3 GPI PD I L I2S_1_SDI PCM_1_SIN AC97SDI G E Ret_IO NC Xi2s1SDO GPC0 4 GPI PD I L I2S_1_SDO PCM_1_SOUT AC97SDO G E Ret_IO NC Xpcm2SCLK GPC1 0 GPI PD I L...

Page 12: ... I2S_2_SDI G E Ret_IO NC Xpcm2SOUT GPC1 4 GPI PD I L PCM_2_SOUT I2S_2_SDO G E Ret_IO NC XpwmTOUT 0 GPD0 0 GPI PD I L TOUT_0 G E Ret_IO NC XpwmTOUT 1 GPD0 1 GPI PD I L TOUT_1 G E Ret_IO NC XpwmTOUT 2 GPD0 2 GPI PD I L TOUT_2 G E Ret_IO NC XpwmTOUT 3 GPD0 3 GPI PD I L TOUT_3 PWM_MIE PWM_M DNIE G E Ret_IO NC MIE PWM control Xi2c0SDA GPD1 0 GPI PD I L I2C0_SDA G E Ret_IO NC VDD_EXT0 Xi2c0SCL GPD1 1 GP...

Page 13: ... I2C2_SDA IEM_SCLK G E Ret_IO NC Xi2c2SCL GPD1 5 GPI PD I L I2C2_SCL IEM_SPWI G E Ret_IO NC XciPCLK GPE0 0 GPI PD I L CAM_A_PCLK G E Ret_IO NC XciVSYNC GPE0 1 GPI PD I L CAM_A_VSYNC G E Ret_IO NC XciHREF GPE0 2 GPI PD I L CAM_A_HREF G E Ret_IO NC XciDATA 0 GPE0 3 GPI PD I L CAM_A_DATA 0 G E Ret_IO NC XciDATA 1 GPE0 4 GPI PD I L CAM_A_DATA 1 G E Ret_IO NC XciDATA 2 GPE0 5 GPI PD I L CAM_A_DATA 2 G ...

Page 14: ... NC XciDATA 6 GPE1 1 GPI PD I L CAM_A_DATA 6 G E Ret_IO NC XciDATA 7 GPE1 2 GPI PD I L CAM_A_DATA 7 G E Ret_IO NC XciCLKenb GPE1 3 GPI PD I L CAM_A_CLKOU T G E Ret_IO NC XciFIELD GPE1 4 GPI PD I L CAM_A_FIELD G E Ret_IO NC XvHSYNC GPF0 0 GPI PD I L LCD_HSYNC SYS_CS0 VEN_HSYNC G E Ret_IO NC XvVSYNC GPF0 1 GPI PD I L LCD_VSYNC SYS_CS1 VEN_VSYNC G E Ret_IO NC XvVDEN GPF0 2 GPI PD I L LCD_VDEN SYS_RS ...

Page 15: ..._DATA 2 G E Ret_IO NC XvVD 3 GPF0 7 GPI PD I L LCD_VD 3 SYS_VD 3 VEN_DATA 3 G E Ret_IO NC XvVD 4 GPF1 0 GPI PD I L LCD_VD 4 SYS_VD 4 VEN_DATA 4 G E Ret_IO NC XvVD 5 GPF1 1 GPI PD I L LCD_VD 5 SYS_VD 5 VEN_DATA 5 G E Ret_IO NC XvVD 6 GPF1 2 GPI PD I L LCD_VD 6 SYS_VD 6 VEN_DATA 6 G E Ret_IO NC XvVD 7 GPF1 3 GPI PD I L LCD_VD 7 SYS_VD 7 VEN_DATA 7 G E Ret_IO NC XvVD 8 GPF1 4 GPI PD I L LCD_VD 8 SYS_...

Page 16: ...et_IO NC XvVD 13 GPF2 1 GPI PD I L LCD_VD 13 SYS_VD 13 V656_DATA 5 G E Ret_IO NC XvVD 14 GPF2 2 GPI PD I L LCD_VD 14 SYS_VD 14 V656_DATA 6 G E Ret_IO NC XvVD 15 GPF2 3 GPI PD I L LCD_VD 15 SYS_VD 15 V656_DATA 7 G E Ret_IO NC XvVD 16 GPF2 4 GPI PD I L LCD_VD 16 SYS_VD 16 G E Ret_IO NC XvVD 17 GPF2 5 GPI PD I L LCD_VD 17 SYS_VD 17 G E Ret_IO NC XvVD 18 GPF2 6 GPI PD I L LCD_VD 18 SYS_VD 18 G E Ret_I...

Page 17: ... 22 G E Ret_IO NC XvVD 23 GPF3 3 GPI PD I L LCD_VD 23 SYS_VD 23 V656_CLK G E Ret_IO NC XvVSYNC_L DI GPF3 4 GPI PD I L VSYNC_LDI VSYNC_LDI VSYNC_LDI G E Ret_IO NC XvSYS_OE GPF3 5 GPI PD I L SYS_OE SYS_OE VEN_FIELD G E Ret_IO NC Xmmc0CLK GPG0 0 GPI PD I L SD_0_CLK G E Ret_MM C NC Xmmc0CMD GPG0 1 GPI PD I L SD_0_CMD G E Ret_MM C NC Xmmc0CDn GPG0 2 GPI PD I L SD_0_CDn G E Ret_MM C NC Xmmc0DATA 0 GPG0 ...

Page 18: ...I PD I L SD_0_DATA 3 G E Ret_MM C NC Xmmc1CLK GPG1 0 GPI PD I L SD_1_CLK G E Ret_MM C NC Xmmc1CMD GPG1 1 GPI PD I L SD_1_CMD G E Ret_MM C NC Xmmc1CDn GPG1 2 GPI PD I L SD_1_CDn G E Ret_MM C NC Xmmc1DATA 0 GPG1 3 GPI PD I L SD_1_DATA 0 SD_0_DATA 4 G E Ret_MM C NC Xmmc1DATA 1 GPG1 4 GPI PD I L SD_1_DATA 1 SD_0_DATA 5 G E Ret_MM C NC Xmmc1DATA 2 GPG1 5 GPI PD I L SD_1_DATA 2 SD_0_DATA 6 G E Ret_MM C ...

Page 19: ...CLK G E Ret_MM C NC Xmmc2CMD GPG2 1 GPI PD I L SD_2_CMD G E Ret_MM C NC Xmmc2CDn GPG2 2 GPI PD I L SD_2_CDn G E Ret_MM C NC Xmmc2DATA 0 GPG2 3 GPI PD I L SD_2_DATA 0 G E Ret_MM C NC Xmmc2DATA 1 GPG2 4 GPI PD I L SD_2_DATA 1 G E Ret_MM C NC Xmmc2DATA 2 GPG2 5 GPI PD I L SD_2_DATA 2 G E Ret_MM C NC VDD_EXT1 Xmmc2DATA 3 GPG2 6 GPI PD I L SD_2_DATA 3 G E Ret_MM C NC VDD_EXT2 Xmmc3CLK GPG3 0 GPI PD I L...

Page 20: ... PD I L SD_3_CDn G E Ret_MM C NC Xmmc3DATA 0 GPG3 3 GPI PD I L SD_3_DATA 0 SD_2_DATA 4 G E Ret_MM C NC Xmmc3DATA 1 GPG3 4 GPI PD I L SD_3_DATA 1 SD_2_DATA 5 G E Ret_MM C NC Xmmc3DATA 2 GPG3 5 GPI PD I L SD_3_DATA 2 SD_2_DATA 6 G E Ret_MM C NC Xmmc3DATA 3 GPG3 6 GPI PD I L SD_3_DATA 3 SD_2_DATA 7 G E Ret_MM C NC XEINT 0 GPH0 0 GPI PD I L G E W No_Ret NC Can be used as a PS_HOLD pin Wakeup source VD...

Page 21: ...o_Ret NC wakeup source XEINT 3 GPH0 3 GPI PD I L G E W No_Ret NC wakeup source XEINT 4 GPH0 4 GPI PD I L G E W No_Ret NC wakeup source XEINT 5 GPH0 5 GPI PD I L G E W No_Ret NC wakeup source XEINT 6 GPH0 6 GPI PD I L G E W No_Ret NC wakeup source XEINT 7 GPH0 7 GPI PD I L G E W No_Ret NC wakeup source XEINT 8 GPH1 0 GPI PD I L G E W No_Ret NC wakeup source VDD_SYS1 XEINT 9 GPH1 1 GPI PD I L G E W ...

Page 22: ... W No_Ret NC wakeup source XEINT 12 GPH1 4 GPI PD I L HDMI_CEC G E W No_Ret NC wakeup source XEINT 13 GPH1 5 GPI PD I L HDMI_HPD G E W No_Ret NC wakeup source XEINT 14 GPH1 6 GPI PD I L G E W No_Ret NC wakeup source XEINT 15 GPH1 7 GPI PD I L G E W No_Ret NC wakeup source XEINT 16 GPH2 0 GPI PD I L KP_COL 0 G E W No_Ret NC wakeup source XEINT 17 GPH2 1 GPI PD I L KP_COL 1 G E W No_Ret NC wakeup so...

Page 23: ...INT 20 GPH2 4 GPI PD I L KP_COL 4 G E W No_Ret NC wakeup source XEINT 21 GPH2 5 GPI PD I L KP_COL 5 G E W No_Ret NC wakeup source XEINT 22 GPH2 6 GPI PD I L KP_COL 6 G E W No_Ret NC wakeup source XEINT 23 GPH2 7 GPI PD I L KP_COL 7 G E W No_Ret NC wakeup source XEINT 24 GPH3 0 GPI PD I L KP_ROW 0 G E W No_Ret NC wakeup source XEINT 25 GPH3 1 GPI PD I L KP_ROW 1 G E W No_Ret NC wakeup source XEINT ...

Page 24: ... source XEINT 28 GPH3 4 GPI PD I L KP_ROW 4 G E W No_Ret NC wakeup source XEINT 29 GPH3 5 GPI PD I L KP_ROW 5 G E W No_Ret NC wakeup source XEINT 30 GPH3 6 GPI PD I L KP_ROW 6 G E W No_Ret NC wakeup source XEINT 31 GPH3 7 GPI PD I L KP_ROW 7 G E W No_Ret NC wakeup source Xi2s0SCLK GPI 0 Func 0 PD O L I2S_0_SCLK PCM_0_SCLK DS Ret_IO sleep NC For low power audio VDD_AUD Xi2s0CDCL K GPI 1 Func 0 PD O...

Page 25: ...used as GPIO EINT Xi2s0SDI GPI 3 Func 0 PD I L I2S_0_SDI PCM_0_SIN DS Ret_IO sleep NC Xi2s0SDO 0 GPI 4 Func 0 PD O L I2S_0_SDO 0 PCM_0_SOUT DS Ret_IO sleep NC Xi2s0SDO 1 GPI 5 Func 0 PD O L I2S_0_SDO 1 DS Ret_IO sleep NC Xi2s0SDO 2 GPI 6 Func 0 PD O L I2S_0_SDO 2 DS Ret_IO sleep NC XmsmADDR 0 GPJ0 0 GPI PD I L MSM_ADDR 0 CAM_B_DATA 0 CF_ADDR 0 MIPI_BYTE_C LK G E Ret_CF NC VDD_MODE M XmsmADDR GPJ0 ...

Page 26: ...RDY TS_SYNC G E Ret_CF NC XmsmADDR 4 GPJ0 4 GPI PD I L MSM_ADDR 4 CAM_B_DATA 4 CF_INTRQ TS_VAL G E Ret_CF NC XmsmADDR 5 GPJ0 5 GPI PD I L MSM_ADDR 5 CAM_B_DATA 5 CF_DMARQ TS_DATA G E Ret_CF NC XmsmADDR 6 GPJ0 6 GPI PD I L MSM_ADDR 6 CAM_B_DATA 6 CF_DRESETN TS_ERROR G E Ret_CF NC XmsmADDR 7 GPJ0 7 GPI PD I L MSM_ADDR 7 CAM_B_DATA 7 CF_DMACKN MHL_D0 G E Ret_CF NC XmsmADDR 8 GPJ1 0 GPI PD I L MSM_ADD...

Page 27: ...DDR 12 GPJ1 4 GPI PD I L MSM_ADDR 12 CAM_B_CLKOU T SROM_ADDR 2 0 MHL_D5 G E Ret_CF NC XmsmADDR 13 GPJ1 5 GPI PD I L MSM_ADDR 13 KP_COL 0 SROM_ADDR 2 1 MHL_D6 G E Ret_CF NC XmsmDATA 0 GPJ2 0 GPI PD I L MSM_DATA 0 KP_COL 1 CF_DATA 0 MHL_D7 G E Ret_CF NC XmsmDATA 1 GPJ2 1 GPI PD I L MSM_DATA 1 KP_COL 2 CF_DATA 1 MHL_D8 G E Ret_CF NC XmsmDATA 2 GPJ2 2 GPI PD I L MSM_DATA 2 KP_COL 3 CF_DATA 2 MHL_D9 G ...

Page 28: ...DATA 6 MHL_D13 G E Ret_CF NC XmsmDATA 7 GPJ2 7 GPI PD I L MSM_DATA 7 KP_ROW 0 CF_DATA 7 MHL_D14 G E Ret_CF NC XmsmDATA 8 GPJ3 0 GPI PD I L MSM_DATA 8 KP_ROW 1 CF_DATA 8 MHL_D15 G E Ret_CF NC XmsmDATA 9 GPJ3 1 GPI PD I L MSM_DATA 9 KP_ROW 2 CF_DATA 9 MHL_D16 G E Ret_CF NC XmsmDATA 10 GPJ3 2 GPI PD I L MSM_DATA 10 KP_ROW 3 CF_DATA 10 MHL_D17 G E Ret_CF NC XmsmDATA 11 GPJ3 3 GPI PD I L MSM_DATA 11 KP...

Page 29: ...GPJ3 7 GPI PD I L MSM_DATA 15 KP_ROW 8 CF_DATA 15 MHL_D22 G E Ret_CF NC XmsmCSn GPJ4 0 GPI PD I L MSM_CSn KP_ROW 9 CF_CSn 0 MHL_D23 G E Ret_CF NC XmsmWEn GPJ4 1 GPI PD I L MSM_WEn KP_ROW 10 CF_CSn 1 MHL_HSYNC G E Ret_CF NC XmsmRn GPJ4 2 GPI PD I L MSM_Rn KP_ROW 11 CF_IORN MHL_IDCK G E Ret_CF NC XmsmIRQn GPJ4 3 GPI PD I L MSM_IRQn KP_ROW 12 CF_IOWN MHL_VSYNC G E Ret_CF NC XmsmADVN GPJ4 4 GPI PD I L...

Page 30: ...1 O H SROM_CSn 3 NFCSn 1 G Ret_aut o NC Xm0CSn 4 MP0_1 4 Func 3 O H SROM_CSn 4 NFCSn 2 ONANDXL_CSn 0 I Ret_aut o Should be connected to CE signal of OneNAND Externally Xm0CSn 5 MP0_1 5 Func 3 O H SROM_CSn 5 NFCSn 3 ONANDXL_CSn 1 G Ret_aut o NC Xm0OEn MP0_1 6 Func 0 O H EBI_OEn I Ret_aut o Xm0WEn MP0_1 7 Func 0 O H EBI_WEn I Ret_aut o Internally connected to OneNAND Xm0BEn 0 MP0_2 0 Func 0 O H EBI_...

Page 31: ...O L EBI_DATA_RD n G Ret_aut o NC Xm0FCLE MP0_3 0 Func 3 O L NF_CLE ONANDXL_ADD RVALID I Ret_aut o Xm0FALE MP0_3 1 Func 3 O L NF_ALE ONANDXL_SMC LK I Ret_aut o Xm0FWEn MP0_3 2 Func 3 O H NF_FWEn ONANDXL_RPn I Ret_aut o Internally connected to OneNAND Xm0FREn MP0_3 3 Func 0 O H NF_FREn G Ret_aut o NC Xm0FRnB 0 MP0_3 4 Func 3 I NF_RnB 0 ONANDXL_INT 0 I Ret_aut o Internally connected to OneNAND Xm0FRn...

Page 32: ...c 0 I NF_RnB 3 G Ret_aut o NC Xm0ADDR 0 MP0_4 0 Func 0 O L EBI_ADDR 0 G Ret_aut o NC Xm0ADDR 1 MP0_4 1 Func 0 O L EBI_ADDR 1 G Ret_aut o NC Xm0ADDR 2 MP0_4 2 Func 0 O L EBI_ADDR 2 G Ret_aut o NC Xm0ADDR 3 MP0_4 3 Func 0 O L EBI_ADDR 3 G Ret_aut o NC Xm0ADDR 4 MP0_4 4 Func 0 O L EBI_ADDR 4 G Ret_aut o NC Xm0ADDR 5 MP0_4 5 Func 0 O L EBI_ADDR 5 G Ret_aut o NC Xm0ADDR 6 MP0_4 6 Func 0 O L EBI_ADDR 6 ...

Page 33: ...DDR 8 MP0_5 0 Func 0 O L EBI_ADDR 8 G Ret_aut o NC Xm0ADDR 9 MP0_5 1 Func 0 O L EBI_ADDR 9 G Ret_aut o NC Xm0ADDR 1 0 MP0_5 2 Func 0 O L EBI_ADDR 10 G Ret_aut o NC Xm0ADDR 1 1 MP0_5 3 Func 0 O L EBI_ADDR 11 G Ret_aut o NC Xm0ADDR 1 2 MP0_5 4 Func 0 O L EBI_ADDR 12 G Ret_aut o NC Xm0ADDR 1 3 MP0_5 5 Func 0 O L EBI_ADDR 13 G Ret_aut o NC Xm0ADDR 1 4 MP0_5 6 Func 0 O L EBI_ADDR 14 G Ret_aut o NC Xm0A...

Page 34: ... L EBI_DATA 0 I Ret_aut o Xm0DATA 1 MP0_6 1 Func 0 O L EBI_DATA 1 I Ret_aut o Xm0DATA 2 MP0_6 2 Func 0 O L EBI_DATA 2 I Ret_aut o Xm0DATA 3 MP0_6 3 Func 0 O L EBI_DATA 3 I Ret_aut o Xm0DATA 4 MP0_6 4 Func 0 O L EBI_DATA 4 I Ret_aut o Xm0DATA 5 MP0_6 5 Func 0 O L EBI_DATA 5 I Ret_aut o Xm0DATA 6 MP0_6 6 Func 0 O L EBI_DATA 6 I Ret_aut o Xm0DATA 7 MP0_6 7 Func 0 O L EBI_DATA 7 I Ret_aut o Internally...

Page 35: ...P0_7 1 Func 0 O L EBI_DATA 9 I Ret_aut o Xm0DATA 1 0 MP0_7 2 Func 0 O L EBI_DATA 10 I Ret_aut o Xm0DATA 1 1 MP0_7 3 Func 0 O L EBI_DATA 11 I Ret_aut o Xm0DATA 1 2 MP0_7 4 Func 0 O L EBI_DATA 12 I Ret_aut o Xm0DATA 1 3 MP0_7 5 Func 0 O L EBI_DATA 13 I Ret_aut o Xm0DATA 1 4 MP0_7 6 Func 0 O L EBI_DATA 14 I Ret_aut o Xm0DATA 1 5 MP0_7 7 Func 0 O L EBI_DATA 15 I Ret_aut o VDD_M1 Xm1ADDR 0 MP1_0 0 Func...

Page 36: ...0 O L LD0_ADDR 1 I X Ret_aut o Xm1ADDR 2 MP1_0 2 Func 0 O L LD0_ADDR 2 I X Ret_aut o Xm1ADDR 3 MP1_0 3 Func 0 O L LD0_ADDR 3 I X Ret_aut o Xm1ADDR 4 MP1_0 4 Func 0 O L LD0_ADDR 4 I X Ret_aut o Xm1ADDR 5 MP1_0 5 Func 0 O L LD0_ADDR 5 I X Ret_aut o Xm1ADDR 6 MP1_0 6 Func 0 O L LD0_ADDR 6 I X Ret_aut o Xm1ADDR 7 MP1_0 7 Func 0 O L LD0_ADDR 7 I X Ret_aut o Xm1ADDR 8 MP1_1 0 Func 0 O L LD0_ADDR 8 I X R...

Page 37: ... Xm1ADDR 1 0 MP1_1 2 Func 0 O L LD0_ADDR 10 I X Ret_aut o Xm1ADDR 1 1 MP1_1 3 Func 0 O L LD0_ADDR 11 I X Ret_aut o Xm1ADDR 1 2 MP1_1 4 Func 0 O L LD0_ADDR 12 I X Ret_aut o Xm1ADDR 1 3 MP1_1 5 Func 0 O L LD0_ADDR 13 I X Ret_aut o Xm1ADDR 1 4 MP1_1 6 Func 0 O L LD0_ADDR 14 I X Ret_aut o Xm1ADDR 1 5 MP1_1 7 Func 0 O L LD0_ADDR 15 I X Ret_aut o Xm1DATA 0 MP1_2 0 Func 0 I LD0_DATA 0 I X Ret_aut o Xm1DA...

Page 38: ...P1_2 2 Func 0 I LD0_DATA 2 I X Ret_aut o Xm1DATA 3 MP1_2 3 Func 0 I LD0_DATA 3 I X Ret_aut o Xm1DATA 4 MP1_2 4 Func 0 I LD0_DATA 4 I X Ret_aut o Xm1DATA 5 MP1_2 5 Func 0 I LD0_DATA 5 I X Ret_aut o Xm1DATA 6 MP1_2 6 Func 0 I LD0_DATA 6 I X Ret_aut o Xm1DATA 7 MP1_2 7 Func 0 I LD0_DATA 7 I X Ret_aut o Xm1DATA 8 MP1_3 0 Func 0 I LD0_DATA 8 I X Ret_aut o Xm1DATA 9 MP1_3 1 Func 0 I LD0_DATA 9 I X Ret_a...

Page 39: ...ut o Xm1DATA 1 1 MP1_3 3 Func 0 I LD0_DATA 11 I X Ret_aut o Xm1DATA 1 2 MP1_3 4 Func 0 I LD0_DATA 12 I X Ret_aut o Xm1DATA 1 3 MP1_3 5 Func 0 I LD0_DATA 13 I X Ret_aut o Xm1DATA 1 4 MP1_3 6 Func 0 I LD0_DATA 14 I X Ret_aut o Xm1DATA 1 5 MP1_3 7 Func 0 I LD0_DATA 15 I X Ret_aut o Xm1DATA 1 6 MP1_4 0 Func 0 I LD0_DATA 16 I X Ret_aut o Xm1DATA 1 7 MP1_4 1 Func 0 I LD0_DATA 17 I X Ret_aut o Xm1DATA 1 ...

Page 40: ...nc 0 I LD0_DATA 19 I X Ret_aut o Xm1DATA 2 0 MP1_4 4 Func 0 I LD0_DATA 20 I X Ret_aut o Xm1DATA 2 1 MP1_4 5 Func 0 I LD0_DATA 21 I X Ret_aut o Xm1DATA 2 2 MP1_4 6 Func 0 I LD0_DATA 22 I X Ret_aut o Xm1DATA 2 3 MP1_4 7 Func 0 I LD0_DATA 23 I X Ret_aut o Xm1DATA 2 4 MP1_5 0 Func 0 I LD0_DATA 24 I X Ret_aut o Xm1DATA 2 5 MP1_5 1 Func 0 I LD0_DATA 25 I X Ret_aut o Xm1DATA 2 6 MP1_5 2 Func 0 I LD0_DATA...

Page 41: ...I X Ret_aut o Xm1DATA 2 8 MP1_5 4 Func 0 I LD0_DATA 28 I X Ret_aut o Xm1DATA 2 9 MP1_5 5 Func 0 I LD0_DATA 29 I X Ret_aut o Xm1DATA 3 0 MP1_5 6 Func 0 I LD0_DATA 30 I X Ret_aut o Xm1DATA 3 1 MP1_5 7 Func 0 I LD0_DATA 31 I X Ret_aut o Xm1DQS 0 MP1_6 0 Func 0 I LD0_DQS 0 I X Ret_aut o Xm1DQS 1 MP1_6 1 Func 0 I LD0_DQS 1 I X Ret_aut o Xm1DQS 2 MP1_6 2 Func 0 I LD0_DQS 2 I X Ret_aut o Xm1DQS 3 MP1_6 3...

Page 42: ...P1_6 4 Func 0 I LD0_DQSn 0 I X Ret_aut o Xm1DQSn 1 MP1_6 5 Func 0 I LD0_DQSn 1 I X Ret_aut o Xm1DQSn 2 MP1_6 6 Func 0 I LD0_DQSn 2 I X Ret_aut o Xm1DQSn 3 MP1_6 7 Func 0 I LD0_DQSn 3 I X Ret_aut o Xm1DQM 0 MP1_7 0 Func 0 O L LD0_DQM 0 I X Ret_aut o Xm1DQM 1 MP1_7 1 Func 0 O L LD0_DQM 1 I X Ret_aut o Xm1DQM 2 MP1_7 2 Func 0 O L LD0_DQM 2 I X Ret_aut o Xm1DQM 3 MP1_7 3 Func 0 O L LD0_DQM 3 I X Ret_a...

Page 43: ...CKE 0 I X Ret_aut o Xm1CKE 1 MP1_7 5 Func 0 O L LD0_CKE 1 I X Ret_aut o Xm1SCLK MP1_7 6 Func 0 O L LD0_SCLK I X Ret_aut o Xm1nSCLK MP1_7 7 Func 0 O H LD0_nSCLK I X Ret_aut o Xm1CSn 0 MP1_8 0 Func 0 O H LD0_CSn_0 I X Ret_aut o Xm1CSn 1 MP1_8 1 Func 0 O H LD0_CSn_1 I X Ret_aut o Xm1RASn MP1_8 2 Func 0 O H LD0_RASn I X Ret_aut o Xm1CASn MP1_8 3 Func 0 O H LD0_CASn I X Ret_aut o Xm1WEn MP1_8 4 Func O ...

Page 44: ...0 I X Ret_aut o Xm2ADDR 1 MP2_0 1 Func 0 O L LD1_ADDR 1 I X Ret_aut o Xm2ADDR 2 MP2_0 2 Func 0 O L LD1_ADDR 2 I X Ret_aut o Xm2ADDR 3 MP2_0 3 Func 0 O L LD1_ADDR 3 I X Ret_aut o Xm2ADDR 4 MP2_0 4 Func 0 O L LD1_ADDR 4 I X Ret_aut o Xm2ADDR 5 MP2_0 5 Func 0 O L LD1_ADDR 5 I X Ret_aut o Xm2ADDR 6 MP2_0 6 Func 0 O L LD1_ADDR 6 I X Ret_aut o VDD_M2 Xm2ADDR 7 MP2_0 7 Func 0 O L LD1_ADDR 7 I X Ret_aut o...

Page 45: ...Xm2ADDR 9 MP2_1 1 Func 0 O L LD1_ADDR 9 I X Ret_aut o Xm2ADDR 1 0 MP2_1 2 Func 0 O L LD1_ADDR 10 I X Ret_aut o Xm2ADDR 1 1 MP2_1 3 Func 0 O L LD1_ADDR 11 I X Ret_aut o Xm2ADDR 1 2 MP2_1 4 Func 0 O L LD1_ADDR 12 I X Ret_aut o Xm2ADDR 1 3 MP2_1 5 Func 0 O L LD1_ADDR 13 I X Ret_aut o Xm2ADDR 1 4 MP2_1 6 Func 0 O L LD1_ADDR 14 I X Ret_aut o Xm2ADDR 1 5 MP2_1 7 Func 0 O L LD1_ADDR 15 I X Ret_aut o Xm2D...

Page 46: ...P2_2 1 Func 0 I LD1_DATA 1 I X Ret_aut o Xm2DATA 2 MP2_2 2 Func 0 I LD1_DATA 2 I X Ret_aut o Xm2DATA 3 MP2_2 3 Func 0 I LD1_DATA 3 I X Ret_aut o Xm2DATA 4 MP2_2 4 Func 0 I LD1_DATA 4 I X Ret_aut o Xm2DATA 5 MP2_2 5 Func 0 I LD1_DATA 5 I X Ret_aut o Xm2DATA 6 MP2_2 6 Func 0 I LD1_DATA 6 I X Ret_aut o Xm2DATA 7 MP2_2 7 Func 0 I LD1_DATA 7 I X Ret_aut o Xm2DATA 8 MP2_3 0 Func 0 I LD1_DATA 8 I X Ret_a...

Page 47: ...t o Xm2DATA 1 0 MP2_3 2 Func 0 I LD1_DATA 10 I X Ret_aut o Xm2DATA 1 1 MP2_3 3 Func 0 I LD1_DATA 11 I X Ret_aut o Xm2DATA 1 2 MP2_3 4 Func 0 I LD1_DATA 12 I X Ret_aut o Xm2DATA 1 3 MP2_3 5 Func 0 I LD1_DATA 13 I X Ret_aut o Xm2DATA 1 4 MP2_3 6 Func 0 I LD1_DATA 14 I X Ret_aut o Xm2DATA 1 5 MP2_3 7 Func 0 I LD1_DATA 15 I X Ret_aut o Xm2DATA 1 6 MP2_4 0 Func 0 I LD1_DATA 16 I X Ret_aut o Xm2DATA 1 M...

Page 48: ...nc 0 I LD1_DATA 18 I X Ret_aut o Xm2DATA 1 9 MP2_4 3 Func 0 I LD1_DATA 19 I X Ret_aut o Xm2DATA 2 0 MP2_4 4 Func 0 I LD1_DATA 20 I X Ret_aut o Xm2DATA 2 1 MP2_4 5 Func 0 I LD1_DATA 21 I X Ret_aut o Xm2DATA 2 2 MP2_4 6 Func 0 I LD1_DATA 22 I X Ret_aut o Xm2DATA 2 3 MP2_4 7 Func 0 I LD1_DATA 23 I X Ret_aut o Xm2DATA 2 4 MP2_5 0 Func 0 I LD1_DATA 24 I X Ret_aut o Xm2DATA 2 5 MP2_5 1 Func 0 I LD1_DATA...

Page 49: ...X Ret_aut o Xm2DATA 2 7 MP2_5 3 Func 0 I LD1_DATA 27 I X Ret_aut o Xm2DATA 2 8 MP2_5 4 Func 0 I LD1_DATA 28 I X Ret_aut o Xm2DATA 2 9 MP2_5 5 Func 0 I LD1_DATA 29 I X Ret_aut o Xm2DATA 3 0 MP2_5 6 Func 0 I LD1_DATA 30 I X Ret_aut o Xm2DATA 3 1 MP2_5 7 Func 0 I LD1_DATA 31 I X Ret_aut o Xm2DQS 0 MP2_6 0 Func 0 I LD1_DQS 0 I X Ret_aut o Xm2DQS 1 MP2_6 1 Func 0 I LD1_DQS 1 I X Ret_aut o Xm2DQS 2 MP2_...

Page 50: ...P2_6 3 Func 0 I LD1_DQS 3 I X Ret_aut o Xm2DQSn 0 MP2_6 4 Func 0 I LD1_DQSn 0 I X Ret_aut o Xm2DQSn 1 MP2_6 5 Func 0 I LD1_DQSn 1 I X Ret_aut o Xm2DQSn 2 MP2_6 6 Func 0 I LD1_DQSn 2 I X Ret_aut o Xm2DQSn 3 MP2_6 7 Func 0 I LD1_DQSn 3 I X Ret_aut o Xm2DQM 0 MP2_7 0 Func 0 O L LD1_DQM 0 I X Ret_aut o Xm2DQM 1 MP2_7 1 Func 0 O L LD1_DQM 1 I X Ret_aut o Xm2DQM 2 MP2_7 2 Func 0 O L LD1_DQM 2 I X Ret_au...

Page 51: ...M 3 I X Ret_aut o Xm2CKE 0 MP2_7 4 Func 0 O L LD1_CKE 0 I X Ret_aut o Xm2CKE 1 MP2_7 5 Func 0 O L LD1_CKE 1 I X Ret_aut o Xm2SCLK MP2_7 6 Func 0 O L LD1_SCLK I X Ret_aut o Xm2nSCLK MP2_7 7 Func 0 O H LD1_nSCLK I X Ret_aut o Xm2CSn 0 MP2_8 0 Func 0 O H LD1_CSn_0 I X Ret_aut o Xm2CSn 1 MP2_8 1 Func 0 O H LD1_CSn_1 I X Ret_aut o Xm2RASn MP2_8 2 Func 0 O H LD1_RASn I X Ret_aut o Xm2CASn MP2_8 3 Func O...

Page 52: ...2_8 4 Func 0 O H LD1_WEn I X Ret_aut o XjTRSTn ETC0 0 PD I L XjTRSTn DS Ret_aut o NC Internally connected to Pd resistor XjTMS ETC0 1 PU I H XjTMS DS Ret_aut o NC Internally connected to Pu resistor XjTCK ETC0 2 PD I L XjTCK DS Ret_aut o NC Internally connected to Pd resistor XjTDI ETC0 3 PU I H XjTDI DS Ret_aut o NC Internally connected to Pu resistor VDD_SYS0 XjTDO ETC0 4 O L XjTDO DS Ret_aut o ...

Page 53: ...uit guide XjDBGSEL ETC0 5 I XjDBGSEL DS Ret_aut o PD Externally should be connected to pull down resistor or GND XOM 0 ETC1 0 I XOM 0 DS No_Ret PU PD Booting option XOM 1 ETC1 1 I XOM 1 DS No_Ret PU PD OneNAND case OM 5 0 2b 001001 XOM 2 ETC1 2 I XOM 2 DS No_Ret PU PD XOM 3 ETC1 3 I XOM 3 DS No_Ret PU PD XOM 4 ETC1 4 I XOM 4 DS No_Ret PU PD XOM 5 ETC1 5 I XOM 5 DS No_Ret PU PD ...

Page 54: ...DR Low DDR2 LPDDR2 High Should connect to pull down or GND XPWRRGTON ETC1 7 O L XPWRRGTON DS No_Ret NC XnRESET ETC2 0 I XnRESET DS No_Ret PU VDD_AUD XCLKOUT ETC2 1 O L CLKOUT DS No_Ret NC XnRSTOUT ETC2 2 O L XnRSTOUT DS No_Ret NC VDD_SYS0 XnWRESET ETC2 3 PU I H XnWRESET DS No_Ret NC Internally connected to Pu resistor VDD_CKO XRTCCLKO ETC2 4 O L RTC_CLKOUT DS No_Ret NC VDD_SYS0 XuotgDRVV BUS ETC2 ...

Page 55: ... PD XrtcXTI ETC4 0 I XrtcXTI DS No_Ret PD VDD_RTC XrtcXTO ETC4 1 O L XrtcXTO DS No_Ret NC 14pF external cap each pad 10Mohm feedback register between pad XXTI ETC4 2 I XXTI DS No_Ret PD VDD_SYS0 XXTO ETC4 3 O L XXTO DS No_Ret NC 14pF external cap each pad 5Mohm feedback register between pad XusbXTI ETC4 4 I XusbXTI DS No_Ret PD VDD_SYS0 XusbXTO ETC4 5 O L XusbXTO DS No_Ret NC 14pF external cap eac...

Page 56: ... Func 0 Func 1 Func 2 Func 3 AU RET Power down Not Use d Circuit guide XadcAIN 2 ANALOG 2 AIN 2 DS NC XadcAIN 3 ANALOG 3 AIN 3 DS NC XadcAIN 4 ANALOG 4 AIN 4 DS NC XadcAIN 5 ANALOG 5 AIN 5 DS NC XadcAIN 6 ANALOG 6 AIN 6 DS NC XadcAIN 7 ANALOG 7 AIN 7 DS NC XadcAIN 8 ANALOG 8 AIN 8 DS NC XadcAIN 9 ANALOG 9 AIN 9 DS NC ...

Page 57: ...NALOG 1 1 XdacOUT DS NC 75ohm pull down XdacIREF ANALOG 1 4 XdacIREF DS NC 1 2Kohm 1 pull down XdacVREF ANALOG 1 5 XdacVREF DS GN D 100nF GND tie VDD_DAC XdacCOMP ANALOG 1 6 XdacCOMP DS NC 100nF VDD_DAC tie XhdmiTX0P ANALOG 1 7 HDMI_TX0P DS NC XhdmiTX0N ANALOG 1 8 HDMI_TX0N DS NC XhdmiTX1P ANALOG 1 9 HDMI_TX1P DS NC XhdmiTX1N ANALOG 2 0 HDMI_TX1N DS NC VDD_HDMI XhdmiTX2P ANALOG 2 HDMI_TX2P DS NC ...

Page 58: ...TX2N ANALOG 2 2 HDMI_TX2N DS NC XhdmiTXCP ANALOG 2 3 HDMI_TXCP DS NC XhdmiTXCN ANALOG 2 4 HDMI_TXCN DS NC XhdmiREXT ANALOG 2 5 HDMI_REXT DS PD 4 6Kohm 1 pull down XhdmiXTI ANALOG 2 6 HDMI_XI DS PD VDD_HDMI _OSC XhdmiXTO ANALOG 2 7 HDMI_XO DS NC 14pF external cap each pad 5Mohm feedback register between pad XmipiMDP0 ANALOG 2 8 MIPI_MDP_0 DS NC VDD_MIPI _A XmipiMDP1 ANALOG 2 9 MIPI_MDP_1 DS NC ...

Page 59: ... Not Use d Circuit guide XmipiMDP2 ANALOG 3 0 MIPI_MDP_2 DS NC XmipiMDP3 ANALOG 3 1 MIPI_MDP_3 DS NC XmipiMDN0 ANALOG 3 2 MIPI_MDN_0 DS NC XmipiMDN1 ANALOG 3 3 MIPI_MDN_1 DS NC XmipiMDN2 ANALOG 3 4 MIPI_MDN_2 DS NC XmipiMDN3 ANALOG 3 5 MIPI_MDN_3 DS NC XmipiSDP0 ANALOG 3 6 MIPI_SDP_0 DS NC XmipiSDP1 ANALOG 3 7 MIPI_SDP_1 DS NC XmipiSDP2 ANALOG 3 MIPI_SDP_2 DS NC ...

Page 60: ...r down Not Use d Circuit guide 8 XmipiSDP3 ANALOG 3 9 MIPI_SDP_3 DS NC XmipiSDN0 ANALOG 4 0 MIPI_SDN_0 DS NC XmipiSDN1 ANALOG 4 1 MIPI_SDN_1 DS NC XmipiSDN2 ANALOG 4 2 MIPI_SDN_2 DS NC XmipiSDN3 ANALOG 4 3 MIPI_SDN_3 DS NC XmipiMDPC LK ANALOG 4 4 MIPI_CLK_TX _P DS NC XmipiMDNC LK ANALOG 4 5 MIPI_CLK_TX _N DS NC XmipiSDPC LK ANALOG 4 6 MIPI_CLK_RX _P DS NC ...

Page 61: ...7 MIPI_CLK_RX _N DS NC XmipiVREG _0P4V ANALOG 4 8 MIPI_Reg_ca p DS NC 2nF GND tie XuotgDP ANALOG 4 9 XuotgDP DS NC XuotgREXT ANALOG 5 0 XuotgREXT DS NC 44 2ohm 1 pull down VDD_UOTG _A XuotgDM ANALOG 5 1 XuotgDM DS NC XefFSOURC E_0 ANALOG 5 3 efrom_fsour ce_0 DS GN D Should be tied to GND Not pull down XuhostDP ANALOG 5 9 XuhostDP DS NC VDD_UHOS T_A XuhostREX T ANALOG 6 0 XuhostREXT DS NC 44 2ohm 1...

Page 62: ...ower Domain Ball Name Port In Out Pu Pd Rese t stat us Func 0 Func 1 Func 2 Func 3 AU RET Power down Not Use d Circuit guide XuhostDM ANALOG 6 1 XuhostDM DS NC XuotgID ANALOG 6 3 XuotgID DS NC VDD_UOTG _A XuotgVBUS ANALOG 6 4 XuotgVBUS DS NC Xepllfilt er 1 8nF cap ...

Page 63: ...1 AE2 XI2S0SDI A8 XPWMTOUT_2 AA23 XEINT_21 AC13 XURXD_3 AE3 XI2S0LRCK A9 XMMC3CLK AA24 XEINT_12 AC14 XUTXD_2 AE4 XVSYS_OE A10 XMMC3DATA_3 AA25 XEINT_7 AC15 XMIPIVREG_0P4V AE5 XVVD_15 A11 XSPIMOSI_1 AB1 XPCM0FSYNC AC16 XI2C2SDA AE6 XVVD_10 A12 XM1DATA_31 AB2 XPCM0SIN AC17 XUHOSTREXT AE7 XVVD_6 A13 XM1DATA_29 AB3 XI2S1CDCLK AC18 XUOTGVBUS AE8 XMIPISDN3 A14 XM1DATA_26 AB4 XI2S1SDO AC19 XUOTGDRVVBUS A...

Page 64: ... AE22 XI2C2SCL AA3 XI2S0SDO_2 AB18 XDDR2SEL AD8 XMIPISDP3 AE23 XI2C1SDA AA4 XMMC2CDN AB19 XCIFIELD AD9 XMIPISDP2 AE24 XCLKOUT AA5 XI2S1SDI AB20 XCIDATA_2 AD10 XMIPISDPCLK AE25 VSS AA6 XVVD_19 AB21 XCIDATA_4 AD11 XMIPISDP1 B1 XMSMDATA_10 AA7 XVVD_17 AB22 XEINT_25 AD12 XMIPISDP0 B2 XMSMDATA_13 AA8 XVVD_8 AB23 XEINT_31 AD13 XMIPIMDN3 B3 XMSMDATA_14 AA9 XVVD_0 AB24 XEINT_19 AD14 XMIPIMDN2 B4 XMSMWEN A...

Page 65: ...G12 XSPICLK_1 B18 XM1DQS_1 D8 XUTXD_0 E23 XM2DATA_23 G13 XSPIMISO_1 B19 XM1DATA_8 D9 XUCTSN_0 E24 XM2DATA_22 G14 XM1CSN_1 B20 XM1DATA_9 D10 XMMC3CMD E25 XM2DATA_21 G15 XM1CKE_0 B21 XM1DATA_4 D11 XMMC3DATA_2 F1 XMSMADDR_10 G16 XM1CKE_1 B22 XM1DQS_0 D12 XM1DQS_3 F2 XMSMADDR_13 G17 XM1WEN B23 XM1DATA_2 D13 XM1DATA_24 F3 XMSMDATA_0 G18 XM1CSN_0 B24 XM2DATA_31 D14 XM1DQM_2 F4 XM0ADDR_14 G19 VSS B25 XM2...

Page 66: ...SMADDR_3 C13 XM1DATA_27 E3 XMSMDATA_5 F18 XM1ADDR_13 H19 XM2ADDR_9 C14 XM1DATA_23 E4 XMSMADDR_2 F19 XM1ADDR_10 H20 XM2ADDR_13 C15 XM1DATA_19 E5 XMSMADDR_12 F20 XM2ADDR_5 H21 XM2DQM_2 C16 XM1DATA_17 E6 XMMC0CMD F21 XM2ADDR_4 H22 XM2ADDR_6 C17 XM1DATA_15 E7 XMMC1DATA_1 F22 XM2DATA_27 H23 XM2ADDR_11 C18 XM1DATA_12 E8 XPWMTOUT_0 F23 XM2DATA_20 H24 XM2DATA_17 C19 XM1DATA_7 E9 XSPICSN_0 F24 XM2DQS_2 H25...

Page 67: ...4 VDD_M1 L7 XM0ADDR_1 N1 XM0DATA_4 P21 VDD_RTC J15 VDD_M1 L9 VSS N2 XM0DATA_5 P22 XM2WEN J16 VDD_M1 L10 VDD_INT N3 XM0CSN_4 P23 XM2DATA_0 J17 VDD_M2 L11 VDD_INT N4 XM0DATA_7 P24 XM2DATA_3 J19 XM2ADDR_7 L12 VSS N5 XM0DATA_14 P25 XM2DQM_0 J20 XM2ADDR_14 L13 VDD_ARM N6 XM0BEN_1 R1 XHDMITXCN J21 XM2RASN L14 VDD_ARM N7 XM0CSN_5 R2 XHDMITXCP J22 XM2ADDR_12 L15 VDD_ARM N9 XM0CSN_3 R3 XM0FRNB_0 J23 XM2CAS...

Page 68: ...ATA_3 N24 XM2DQS_0 R17 VDD_ALIVE K12 VSS M5 XM0DATA_13 N25 XM2DQSN_0 R19 VSS_EPLL K13 VDD_INT M6 XM0FRNB_1 P1 XM0DATA_6 R20 VDD_EPLL K14 VDD_INT M7 XM0DATA_RDN P2 XM0DATA_15 R21 XEPLLFILTER K15 VDD_INT M9 VDD_M0 P3 XJDBGSEL R22 XRTCCLKO K16 VSS M10 VSS P4 XM0WEN R23 XM2ADDR_3 K17 VDD_M2 M11 VDD_INT P5 XJTRSTN R24 XM2DATA_1 K19 VSS M12 VSS P6 VDD_HDMI R25 XM2DATA_2 K20 XM2ADDR_15 M13 VDD_ARM P7 VSS...

Page 69: ...LK T13 VSS V6 VSS_DAC Y7 XVVD_23 T14 VSS V7 VDD_DAC Y8 XVVD_12 T15 VSS V19 VDD_CAM Y9 XVVD_4 T16 VSS V20 XEINT_8 Y10 XVVSYNC T17 VDD_KEY V21 XEINT_18 Y11 XADCAIN_4 T19 VDD_SYS1 V22 XEINT_9 Y12 XADCAIN_6 T20 XNRSTOUT V23 XOM_2 Y13 VDD_MIPI_A T21 XNWRESET V24 XOM_5 Y14 VSS_UHOST_D T22 XOM_1 V25 XOM_4 Y15 VSS_UOTG_AC T23 XOM_0 W1 XHDMIREXT Y16 VDD_UHOST_A T24 XRTCXTI W2 XM0WAITN Y17 VSS_UOTG_A T25 XR...

Page 70: ...XEINT_10 U7 VDD_DAC_A W10 VDD_ADC Y25 XEINT_3 U9 VDD_AUD W11 VSS_ADC U10 VDD_LCD W12 XADCAIN_5 U11 VSS_MIPI W13 VDD_UHOST_D U12 VDD_MIPI_D W14 VDD_MIPI_PLL U13 VDD_MIPI_D W15 VDD_ALIVE U14 VSS_MIPI W16 VDD_UOTG_A U15 VDD_UOTG_D W17 VSS_UOTG_D U16 VDD_SYS0 W18 VDD_EXT1 U17 VDD_SYS0 W19 VSS U19 VDD_AUD W20 XEINT_15 U20 XEINT_16 W21 XEINT_6 U21 XOM_3 W22 XEINT_11 U22 XPWRRGTON W23 XEINT_2 U23 XNRESET...

Page 71: ... 0 XCIFIELD XCIHREF XCIPCLK XCIVSYNC VDD_AUD XI2S0CDCLK XI2S0LRCK XI2S0SCLK XI2S0SDI XI2S0SDO_ 2 0 XI2S1CDCLK XI2S1LRCK XI2S1SCLK XI2S1SDI XI2S1SDO XPCM2EXTCLK XPCM2FSYNC XPCM2SCLK XPCM2SIN XPCM2SOUT XCLKOUT VDD_MODEM XMSMADDR_ 13 0 XMSMADVN XMSMCSN XMSMDATA_ 15 0 XMSMIRQN XMSMRN XMSMWEN VDD_KEY XEINT_ 31 16 VDD_SYS0 XXTI XXTO XOM_ 5 0 XPWRRGTON XNRESET XNRSTOUT XN WRESET XEINT_ 7 0 XUOTGDRVVBUS X...

Page 72: ...MP XDACIREF XDACOUT_0 XDACVREF VDD_HDMI XHDMIREXT XHDMITX0N XHDMITX0P XHDMITX1N XHDMITX1P XHDMITX2N XHDMITX2P XHDMITXCN XHDMITXCP VDDOSC_HDMI XHDMIXTI XHDMIXTO VDD_MIPI_D XMIPIMDNCLK XMIPIMDPCLK XMIPISDNCLK XMIPISDPCLK XMIPIVREG_0P4V VDD_MIPI_A XMIPIMDN 3 0 XMIPIMDP 3 0 XMIPISDN 3 0 XMIPISDP 3 0 VDD_UOTG_A XUOTGDM XUOTGDP XUOTGID XUOTGREXT XUOTGVBUS VDD_UHOST_A XUHOSTDM XUHOSTDP XUHOSTREXT ANALOG ...

Page 73: ... 1 8 1 9 VDD_SYS0 On On 1 7 1 8 2 5 3 0 3 6 VDD_SYS1 On On 1 7 1 8 2 5 3 0 3 6 VDD_EXT0 On On 1 7 1 8 2 5 3 0 3 6 VDD_EXT1 On On 1 7 1 8 2 5 3 0 3 6 VDD_EXT2 On On 1 7 1 8 2 5 3 0 3 6 VDD_CKO On On 1 7 2 5 3 0 3 6 VDD_RTC On On 1 7 2 5 3 0 3 6 VDD_LCD On On 1 7 2 5 3 0 3 6 VDD_CAM On On 1 7 2 5 3 0 3 6 VDD_AUD On On 1 7 2 5 3 0 3 6 VDD_MODEM On On 1 7 2 5 3 0 3 6 VDD_KEY On On 1 7 2 5 3 0 3 6 VDD_...

Page 74: ...1 1 1 15 VDD_UOTG_A On Off Off 3 0 3 3 3 6 VDDI_UOTG_D On Off Off 1 05 1 1 1 15 VDD_UHOST_A On Off Off 3 0 3 3 3 6 VDDI_UHOST_D On Off Off 1 05 1 1 1 15 Operating Temperature TA Industrial 40 to 85 o C Operating Temperature TA Extended 20 to 70 o C On Must be On the power Off Must be Off the power in the sleep mode On Off On Off can be selected Note 1 VDD_M1 M2 power depends on MCP voltage ...

Page 75: ...annel and I2C 3channel has different Power domains Ex 2 MMC channel 2Uart channel 1 SPI channel 1 I2C channel 1 8V 2MMC channel 2Uart channel 1 SPI channel 2 I2C channel 3 0V VDD_EXT0 1 8V MMC0 1 2channel SPI0 1channel Uart0 1 2channel I2C0 1channel VDD_EXT1 3 0V MMC2 1channel Uart2 3 2channel I2C1 2 2channel VDD_EXT2 3 0V MMC3 1channel SPI1 1channel Ex 4 MMC channel 4Uart channel 2 SPI channel 3 ...

Page 76: ...5PV210_HARDWARE DESING GUIDE REV 1 0 76 3 4 Power On Off Sequence Power On sequence OSC_STABLE 0ns 0ns Figure 3 1 Power on sequence Note 1 OSC s frequency should be meet the specification which is 24Mhz ...

Page 77: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 77 Power Off Sequence Figure 3 2 Power off sequence ...

Page 78: ...ower down mode deep stop top off deep idle top off sleep mode Alive block GPIO GPH0 GPH1 GPH 2 GPH3 is not retention I O After wake up from power down mode you should first set GPIO configuration as the same ones before those power down mode and then you should set ENABLE_GPIO ENABLE_MMC_IO and ENABLE_UART_IO bits to 1 so that normal I O pad can be used When wakeup from power down mode the status ...

Page 79: ...TDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 Cortex A8 Core JTAG 1 Peripherals JTAG Note JTAG signals don t need external pull up down registers Because C110 has internal pull up down registers for JTAG signal RESET ETC Dedicated signal Ball Name I O Description XOM_0 XOM_5 I Operating Mode control signals 6bit XDDR2SEL I Se...

Page 80: ...ut for internal osc circuit XXTO O Crystal output for internal osc circuit XUSBXTI I Crystal Input for internal USB circuit XUSBXTO O Crystal output for internal USB circuit XHDMIXTI I Crystal Input for internal HDMI circuit XHDMIXTO O Crystal output for internal HDMI circuit E fuse Dedicated signal Ball Name I O Description XEFFSOURCE_0 I Power PAD for efuse ROM s FSOURCE Should be tied to GND ...

Page 81: ... X TAL 1 b0 1 b1 1 b1 Nand 2KB 4cycle Nand 8bit ECC X TAL USB 1 b0 X TAL 1 b0 1 b1 iROM NOR boot X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b0 1 b1 1 b1 1 b1 I ROM eMMC 8 bit X TAL USB 1 b0 X TAL 1 b0 1 b1 eSSD X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b1 Nand 2KB 5cycle X TAL USB 1 b0 X TAL 1 b0 1 b1 Nand 4KB 5cycle X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b1 1 b1 Nand 16bit ECC Nand 4KB 5cycle X TAL USB 1 b0 X TAL 1 b0 1 ...

Page 82: ...0CSn4 NFCSn2 ONANDXL_CSn0 signal should be used for boot 2 NAND Using S W 8bit ECC at boot page S5PV210 supports 16bit ECC in case of 4KB 5cycle Nand type Xm0CSn2 NFCSn0 signal should be used for boot 3 SD MMC and eMMC SDMMC CH0 is used for first 4bit boot SDMMC CH2 is used for second boot 4 eMMC boot SD MMC CH0 is used for eMMC boot 4 8 bit Bus width is controlled by OM setting 5 UART boot UART C...

Page 83: ...C Figure 4 1 Input Clock Example CMAIN Depends on Crystal s load capacitance CL CUSB Depends on Crystal s load capacitance CL CHDMI Depends on Crystal s load capacitance CL External capacitance used for X tal CRTC Depends on Crystal s load capacitance CL Rfed _MAIN 5M Ohm Rfed _USB 5M Ohm Rfed _HDMI 5M Ohm Feedback resistor between XTI with XTO Rfed _RTC 10M Ohm ESR 60ohm max Shunt capacitance 7pF...

Page 84: ...following equation CL C1 CIC_IN C2 CIC_OUT CIC_IN C1 C2 CIC_OUT pcb strays assumed to 1 3pF i Load capacitance CL is specified when ordering crystal ii Pin capacitance CIC_IN 1 8 pF Pin capacitance for X tal main usb hdmi CIC_OUT 2 5 pF CIC_IN 1 2 pF Pin capacitance for X tal rtc CIC_OUT 2 5 pF EX If Crystal has CL 14pF then C1 C2 are around 22pF ...

Page 85: ...dress Bank Address CS CKE signals 5 2 TQ Temperature Indicator Samsung mDDR includes the enhanced feature Temperature Indicator TQ which informs MDRAM s internal temperature of controller in order to notice that DRAM inside temperature become higher than 85 C which is the highest temperature guaranteed normally in the specification In over 85 C DRAM refresh cycle is derated according as the temper...

Page 86: ... through power via as short as possible c Pay attention whether power via makes ground plane split or not The value of bypass capacitor is determined by considering impedance profile of power plane and operating frequency And the number of capacitors is as large as possible considering of PCB space Trace routing guide I DQ DQM DQS signal Signals in same group have pattern length matched within 1 5...

Page 87: ...and Control net CKE 1 0 CSn 1 0 ADDR 15 0 RASn CASn WEn ㅤ c Do not route near high speed signals SCLK SCLKn DQS n 3 0 and DATA net or have enough spacing over 3 WIDTH ㅤ d Direct connect GATEI pin B10 to GATEO pin C10 III SCLK SCLKn signal ㅤ a Star topology is recommenced ㅤ b Recommended differential impedance is 100 ohm ㅤ c SCLK SCLKn Skew 10ps Target length 1 0mm ㅤ d SCLK n DQS 3 0 Skew 100ps Tar...

Page 88: ... Enable SROM_WAITn I Memory Port 0 SROM nWait EBI_DATA_RDn O Memory Port 0 SROM OneNAND CF If data is output this signal goes to High If data is input this signal goes to Low EBI_ADDR 15 0 O Memory port 0 Address bus EBI_DATA 15 0 IO Memory port 0 Data bus SRAM ROM S5PV210 8bit data bus A0 Xm0ADDR0 Half word base AddrMode 0 default A0 Xm0ADDR0 Addr connection 16bit data bus Byte base AddrMode 1 A0...

Page 89: ...e Examples Figure 6 1 Memory Interface with 8 bit SRAM Figure 6 2 Memory Interface with 16 bit SRAM Note 1 Xm0ADDR 16 22 are muxed with other functions And Xm0ADDR 16 22 are not released retention automatically like Xm0ADDR 0 15 2 Address space Up to 16MB per Bank ...

Page 90: ...memory write data phase ONANDXL_CSn 1 0 O ONANDXL_CSn 0 1 Chip Select are activated when the address of a memory is within the address region of each bank ONANDXL_CSn 0 1 can be assigned to either SROMC or OneNAND controller by System Controller SFR setting Active LOW ONANDXL_CSn 0 should be connected to OneNand device externally Xm0WEn O Xm0WEn Write Enable indicates that the current bus cycle is...

Page 91: ... 1 ONDXL_SMCLK S5PC110 Figure 7 1 Mux Demux OneNand connection block diagram Note In case of internal OneNand POP ONANDXL_CSn 0 and ONDXL_INT 0 signals are used for internal OneNand If you want to use a external OneNand additionally Only ONANDXL_CSn 1 and ONDXL_INT 1 should be used for it Caution The INT pin of each OneNAND device must be pulled up by an 4 7KOhm external pull up resistor If you wa...

Page 92: ...Read Enalbe NF_RnB 3 0 I Memory Port 0 NAND Flash Ready Busy NF_RnB 0 signal used for iROM boot 4 7Kohm external pull up XM0DATA 15 0 IO Memory port 0 Data bus Xm0nCS 2 NFCSn 0 O Memory Port 0 NAND Chip Select0 Used for iROM boot Xm0nCS 3 NFCSn 1 O Memory Port 0 NAND Chip Select1 Xm0nCS 4 NFCSn 2 O Memory Port 0 NAND Chip Select2 Xm0nCS 5 NFCSn 3 O Memory Port 0 NAND Chip Select3 Xm0nCS2 Xm0nCS3 X...

Page 93: ... 2 4 CE case connection 1 Nand signal power domain belongs to VDD_M0 Confirm the voltage level of another SRAM interface 2 External 4 7K pull up resistor need to be added to RnB signal 3 When NAND is selected for iROM booting storage Xm0CSn2 NFCSn0 Xm0FRnB0 should be used for NAND chip select RnB ...

Page 94: ...if your B d turn on state and CF card inserted after CF controller don t recognize So you have to control the Vdd by GPIO turn off and a few time after turn on 9 2 Signal Description Signal I O Description CF_ADDR 2 0 O CF CARD address for ATAPI CF_IORDY I CF Wait signal from CF card CF_INTRQ I CF Interrupt from CF card CF_DMARQ I CF DMA Request CF_DRESETN O CF DMA Reset CF_DMACKN O CF DMA Acknowl...

Page 95: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 95 9 3 CF 1 slot operation guide ...

Page 96: ...r can use CF card and HDD together by using 2slot operation master and slave 2 Follow Figure 10_2 using 2 slot Schematic master socket is selected by nCSEL_n pin state Master low level Slave NC ex CON1 Master CON2 Slave nCSEL_0 low level nCSEL_1 NC Figure 9 2 2 Slot Operation Schematic example ...

Page 97: ...dth Modulation PWM function which drives an external I O signal The PWM for timer 0 has an optional dead zone generator capability to support a large current device Timer 4 are internal timers without output pins 10 2 Signal Description Signal I O Description TOUT_0 1 2 3 O PWM Timer Output PWM_MIE O PWM output from MIE PWM Usage You can use PWM Usage at below functions LCD back light control Vibr...

Page 98: ... request to send output signal CH0 FIFO Depth 256byte CH1 FIFO Depth 64byte CH2 FIFO Depth 16byte CH3 FIFO Depth 16byte CH2 is for Low Power Audio RP UART2_CTSn and UART2_RTSn signals are muxed with UART3_RXD and UART3_TXD respectively Note 1 Channel 0 1 2 support Auto Flow Control with RTS CTS signal 2 UART Ch 0 1 2 and 3 supports IrDA 1 0 3 UART Ch 2 is used for iROM booting message and iROM UAR...

Page 99: ...L1 2 Xi2cSDA1 2 But this resistor value should be changed by signal bus loading capacitance S5PV210 has 3 IIC control block Channel 1 can use internally for HDMI DDC control Channel 0 and 2 can be used general IIC port But When you use HDM DDC You should not use Channel 1 in general IIC 12 1 Pin Description Signal I O Description Comment Xi2cSCL0 1 2 IO Bus clock Xi2cSDA0 1 2 IO Bus data 1Kohm ext...

Page 100: ... tr Rising time maximum is 300 ns minimum is 20 0 1 Cb bus capacitance 3 When tr Rising time is 300ns SCL might be maximum 13 slower than original setting value 4 To make real SCL within 1 variation of setting value 400kHz tr Rising time should be less than 80nsec 5 User can use this formula to determine Rp Cb and tr Rp Pull up resistance Max is a function of the rise time minimum tr and the estim...

Page 101: ...0 1_MOSI IO SPI master output slave input line 13 2 EXTERNAL Loading Capacitance S5PV210 has three SPI controllers Both controllers should follow the external loading capacitance below Output capacitance must be lower than 30pF at the channel 0 1 13 3 SPI Maximum Speed The maximum frequency Master Tx Master Rx Slave Rx Slave Tx CPHA 0 is up to 50MHz The maximum frequency Slave Tx is up to 20MHz CP...

Page 102: ...lied with 3 3V and VDD_UHOST_D is for USB Host Phy digital power supplied with 1 1V Caution VDD_UHOST_D must be brought up first followed by VDD_UHOST_A in order to limit power consumption and prevent voltage stress on the device 14 3 Circuit Diagram Example To minimize power consumption in USB Host block SEC recommends that user should control powers for VDD_UHOST_A and VDD_UHOST_D 1 use Charge P...

Page 103: ...ucts a guide to integrate a discrete high speed usb device onto a four layer PCB The board design guidelines handle trace separation termination placement requirements and overall trace length guidelines PCB layout guidelines Routing and placement When an engineer lays out a new design the excellent signal quality and minimized EMI problem must be required That is based on four layer board The fir...

Page 104: ... and or duplicate clocks V Route all traces over continuous planes VCC and GND with no interruptions Avoid crossing over anti etch if at all possible VI Ther parallelism between USB differential signals with the trace spacing should be maintained The deviation should be minimized VII The minimized length of high speed clock and periodic signal traces is highly recommended The suggested spacing to ...

Page 105: ...upplied with 3 3V and VDD_UOTG_D_AP is for USB OTG Phy digital power supplied with 1 1V Caution VDD_UOTG_D_AP must be brought up first followed by VDD_UOTG_A_AP in order to limit power consumption and prevent voltage stress on the device Circuit Diagram Example To minimize power consumption in USB OTG block SEC recommends that user should control powers for VDD_UOTG_A_AP and VDD_UOTG_D_AP 1 use Ch...

Page 106: ...US 2 R230 NC R227 0 CON15 USB MINIAB 1 2 3 4 5 9 8 7 6 VBUS D D ID GND G9 G8 G7 G6 U37 TPS2051BDBV 1 2 3 4 5 OUT GND nOC EN IN CTB66 10uF 10V 10K R234 20K XuoDM 2 XuoREXT 2 DC5V XEINT24 KP_ROW0 2 19 R240 0 Figure 15 1 USB OTG Circuit Example Note In this case VBUS signal can be used for wakeup source XEINT 31 0 signals are available ...

Page 107: ...fer on chip and the Modem chip can access that DPSRAM buffer using a typical asynchronous SRAM interface 16 1 Signal Description Signal I O Description XmsmADDR 13 0 I MODEM MSM IF Address XmsmDATA 15 0 IO MODEM MSM IF Data XmsmCSn I MODEM MSM IF Chip Select XmsmWEn I MODEM MSM IF Write enable XmsmREn I MODEM MSM IF Read enable XmsmIRQn O MODEM MSM IF Interrupt to MODEM XmsmADVn I MODEM MSM IF Add...

Page 108: ... request pin from AP to MODEM XmsmIRQn Any other extra interrupt request pin doesn t needs between AP and modem because interrupt requests from modem to AP are delivered through XmsmADDR 12 0 and XmsmDATA 15 0 by writing some value to INT2AP register of DPSRAM in AP 3 Refer the datasheet s timing specification 4 Address connection between MODEM and AP follows the memory controlling policy of MODEM...

Page 109: ...el 3 4 bit mode Not available Every controller has up to 52MHz speed So clock and data line should have same routing path 1 Voltage level should be the same between device and SD MMC IO VDD_EXT0 1 2 Ch 0 1 belongs VDD_EXT0 power domain Ch2 belongs VDD_EXT1 Ch3 belongs VDD_EXT2 2 Add a 10K external pull up resistor to CMD line needs And add 51K external pull up resistors to Data line 3 MMC channel ...

Page 110: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 110 ...

Page 111: ... system clock TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal 18 2 Connection Example Figure 18 1 TSI Connection Example Channel Chip C110 TS CLK TS SYNC TS VAL TS DATA TS ERROR GND TS CLK TS SYNC TS VAL TS DATA TS ERROR GND ...

Page 112: ...ect LCD1 for LCD Indirect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface CPU I F VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertic...

Page 113: ..._7 LCD_VD 7 O SYS_VD 7 IO VEN_DATA 7 O XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA 6 O XVVD_15 LCD_VD 15 O SYS_VD 15 IO V656_...

Page 114: ...R 2 R 1 D 4 D 2 XVVD_19 R 3 R 1 R 0 D 3 D 1 XVVD_18 R 2 R 0 D 2 D 0 XVVD_17 R 1 D 1 XVVD_16 R 0 D 0 XVVD_15 G 7 G 5 G 5 XVVD_14 G 6 G 4 G 4 XVVD_13 G 5 G 3 G 3 XVVD_12 G 4 G 2 G 2 XVVD_11 G 3 G 1 G 1 XVVD_10 G 2 G 0 G 0 XVVD_9 G 1 XVVD_8 G 0 XVVD_7 B 7 B 5 B 4 VEN_DATA 7 XVVD_6 B 6 B 4 B 3 VEN_DATA 6 XVVD_5 B 5 B 3 B 2 VEN_DATA 5 XVVD_4 B 4 B 2 B 1 VEN_DATA 4 XVVD_3 B 3 B 1 B 0 VEN_DATA 3 XVVD_2 B...

Page 115: ... R 6 B 6 R 2 XVVD_13 R 2 R 3 R 5 B 5 R 1 XVVD_12 R 1 R 2 R 4 B 4 R 0 XVVD_11 R 0 R 1 R 3 B 3 G 5 XVVD_10 G 5 R 0 R 2 B 2 G 4 XVVD_9 G 4 G 5 R 1 B 1 G 3 XVVD_8 G 3 G 4 R 5 G 2 R 0 B 0 G 2 XVVD_7 G 2 G 3 R 4 G 1 G 7 G 1 R 4 G 2 XVVD_6 G 1 G 2 R 3 G 0 G 6 G 0 R 3 G 1 XVVD_5 G 0 G 1 R 2 B 5 G 5 B 5 R 2 G 0 XVVD_4 B 4 G 0 R 1 B 4 G 4 B 4 R 1 B 4 XVVD_3 B 3 B 5 R 0 B 3 G 3 B 3 R 0 B 3 XVVD_2 B 2 B 4 G 5...

Page 116: ...A CAM_A B_HREF I Horizontal Sync driven by the Camera processor A CAM_A B_DATA 7 0 I Pixel Data for YCbCr in 8 bit mode or for Y in 16 bit mode driven by the Camera processor A CAM_A B_CLKOUT O Master Clock to the Camera processor A CAM_A B_FIELD I Software Reset or Power Down for the external Camera processor A Note 1 C110 don t have a dedicated CAM RESET signal So GPIO should be allocated for it...

Page 117: ...x Horizontal size Max size Item CAMIF 0 CAMIF 1 CAMIF 2 Scaler input Hsize 4224 4224 1920 Scaler Scaler bypass mode 8192 8192 8192 TargetHsize without output rotation 4224 4224 1920 Output Rotator TargetHsize with output rotation 1920 1920 1280 REAL_WIDTH without input rotation 8192 8192 8192 Input Rotator REAL_HEIGHT with input rotation 1920 1920 1280 20 3 Restriction HREF is valid after VSYNC pu...

Page 118: ...er DATA LANE3 DN for MIPI DPHY XMIPIMDPCLK IO Master CLK Lane DP for MIPI DPHY XMIPIMDNCLK IO Master CLK Lane DN for MIPI DPHY XMIPISDP0 IO Slave DATA LANE0 DP for MIPI DPHY XMIPISDP1 IO Slave DATA LANE1 DP for MIPI DPHY XMIPISDP2 IO Slave DATA LANE2 DP for MIPI DPHY XMIPISDP3 IO Slave DATA LANE3 DP for MIPI DPHY XMIPISDN0 IO Slave DATA LANE0 DN for MIPI DPHY XMIPISDN1 IO Slave DATA LANE1 DN for M...

Page 119: ...on Dp Dn Cable Interface z Routing Length of Dp and Dn have same length between Master and Slave An aberration of them is under 3mm z Maximum Loading capacitance of Cable interface is 70pF z Differential Cable Interface impedance is 100 Ω z It is connected to 2nF Capacitance on XMIPIVREG_0P4V Pin ...

Page 120: ... 0 1uF ceramic capacitor to GND XdacIREF IO External resistor connection Connect 1 2KΩ to GND for full scale output 1 3V Tolerance 1 XdacOUT IO Analog output of DAC Connect 75Ω to GND Tolerance 1 Full scale output current of the DAC is 26 7mA COMPOSITE RCA 1 2 VIDEO GND BAV99LT1 3 2 1 VDD_DAC 75 DACOUT Figure 22 1 TV Encoder connection example XdacIREF VDD_DAC_AP XdacCOMP 1 2K 1 100nF XdacVREF 100...

Page 121: ...HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N TMDS output data pairs XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N TMDS output clock pair XHDMIREXT I HDMI Phy Registance External Reference Resistor 4 6K A 1 resistor is connected to ground HDMI_CEC I O Signal of CEC channel muxed with XEINT12 HDMI_HPD I H...

Page 122: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 122 23 3 Circuit Diagram Example CEC Isolation Circuit 100nF CBL_CEC 1 8K VDD_3V3 SDMP0340LT B C E B C E 0 XEINT12 HDMI_CEC ...

Page 123: ...DS_D2 TMDS_CLK TMDS_SHIELD3 CEC SCL DDC CEC_GND 5V TMDS_CLK HOTPLUG GND4 TMDS_SHIELD2 TMDS_D0 TMDS_D1 TMDS_SHIELD0 NC SDA GND1 GND3 Rclamp0502B N C 1 2 3 HDMI_I2C_EN PCA9517DGK 1 2 3 4 5 6 7 8 VCCA SCLA SDAA GND EN SDAB SCLB VCCB XhdmiTX2N Rclamp0502B N C 1 2 3 4 7K HDMI DC5V HDMI_SDA Rclamp0502B N C 1 2 3 HDMI_SCL Rclamp0502B N C 1 2 3 4 7K 10uF 10V 1K 100nF 10K XhdmiTX1P Xi2cSCL1 XhdmiTXCP VDD_E...

Page 124: ...s most recommended The number of via on the differential line should be minimized pre determined differential line impedance of the differential pairs is 100 Ohm And recommended range of the differential line impedance of the trace is between 95 Ohm to 105 Ohm B Decoupling Capacitor Small size MLCC s are used In all these cases the capacitors should be placed as close as possible to the package Wh...

Page 125: ...lso limits the bandwidth which varies inversely with the square of trace length Do not use any clock signal loops Keep clock lines straight when possible Do not route signals close to the edge of the PCB board Route clock signals on the top layer and make sure that there is no via s Via s change the impedance and introduce more skew and reflections ...

Page 126: ... 0 External Clock Source S5PV210 provides a master clock to the codec through the I2S_CDCLK line This configuration has an advantage that it is not necessary to configure oscillator circuit For the making Master Clock S5PV210 uses and divided EPLL MPLL or PCLK refer to the User s Manual Among these clock sources divided EPLL is used for Lower Power Audio especially If an oscillator circuit is conf...

Page 127: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 127 Connection Example Figure 24 1 IIS Connection Example with WM8580 Master Mode ...

Page 128: ...IIS bus serial data output for channel 2 25 2 External Clock Source S5PV210 provides a master clock to the codec through the Xi2sCDCLK line This configuration has an advantage that it is not necessary to configure oscillator circuit For the making Master Clock S5PV210 uses and divides EPLL MPLL or PCLK refer to the User s Manual If an oscillator circuit is configured for a precise clock for the Sa...

Page 129: ...GUIDE REV 1 0 129 25 3 Connection Example This example shows I2S connection using WM8580 Secondary interface Figure 25 1 IIS Connection Example with WM8580 Master Mode Figure 25 2 External OSC Circuit for IISCDCLK with WM8580 ...

Page 130: ...LK from AC97 CODEC AC97RESETn O nReset for CODEC AC97SYNC O 48KHz Frame SYNC AC97SDI I Serial Data In From AC97 CODEC AC97SDO O Serial Data OUT to AC97 CODEC 26 2 Audio Ports In S5PV210 There is one AC97 Controller AC97 PORT is shared with I2S channel 1 and PCM channel 1 functions 26 3 Connection Example Figure 26 1 AC97 connection example ...

Page 131: ...hift Clock for channel 0 PCM_1_SCLK O PCM Serial Shift Clock for channel 1 PCM_1_EXTCLK I Optional reference clock for channel 1 PCM_1_FSYNC O PCM Sync indicating start of word for channel 1 PCM_1_SIN I PCM Serial Data Input for channel 1 PCM_1_SOUT O PCM Serial Shift Clock for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I Optional reference clock for channel 2 PCM_2_F...

Page 132: ...uit for feeding auxiliary clock 256fs 384fs to Codec chip MCLK please refer to SEC If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks there is a way to accept to this frequency as source of PCM Serial clock and PCM Frame Sync through the XpcmEXTCLK line 27 3 Connection Example This example shows PCM connection using WM8580 Secondar...

Page 133: ...S5PV210_HARDWARE DESING GUIDE REV 1 0 133 Figure 27 1 Internal clocks ex EPLL for PCM master clock with WM8580 Figure 27 2 External clocks ex 2 048MHz for PCM master clock with WM8580 ...

Page 134: ...4 28 SPDIF 28 1 Signal Description Signal I O Description SPDIF_EXTCLK I Global audio main clock External MCLK SPDIF_0_OUT O SPDIFOUT data output Tx only Connection Example This example shows using TOSLINK Figure 28 1 SPDIF Connection Example ...

Page 135: ...erter clock Touch screen interface can control select pads XP XM YP YM of the touch screen for X Y position In S5PV210 There are available two Touch screen interface A mapped with touch signal like bellows AIN 9 XP1 AIN 8 XM1 AIN 7 YP1 AIN 6 YM1 AIN 5 XP0 AIN 4 XM0 AIN 3 YP0 AIN 2 YM0 Note When Touch Screen device is not used XM XP YM or YP can be connected to Analog Input Signal for Normal ADC co...

Page 136: ...to 14 row and 8 columns Keypad signals Key_pad_ROW and Key_pad_COL are multiplexed Host I F and EINT Therefore it is requisite to set GPIO ports as keypad function Refer to GPH2 GPH3 GPJ4 registers Signal I O Description KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 13 0 I KeyIF_Row_data 13 0 Figure 30 1 Multi key input keypad example ...

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