rtd FPGA35S6045HR, User Manual

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4.3 Connectors and Jumpers
P2 & P3: Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connectors P2 and P3 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are
controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx
UCF file with the device pin out.
P2 and P3 are attached to Bank 2 and 0 respectively, and support any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no reference
voltage. This includes LVTTL, LVCMOS33, and LVDS_33 input and output.
Connector P2 also provides a connection to the Xilinx JTAG programming header. This connector header mates with the Xilinx OEM
programming cable through an adapter cable. The adapter cable is provided when purchasing the Starter Kit.
Table 11: P2 and P3 Pin Assignments
IDAN P2 Pin
Signal
Pull
Jmpr CN4
Pin
IDAN P3 Pin
Signal
Pull
Jmpr C9 Pin
Row 1 Row 2 Row 3 Row 1 Row 2 Row 3
1 port0_p[0]
JP1
1 1 port1_p[0]
JP4
1
22 GND 2 22 GND 2
43 port0_n[0] 3 43 port1_n[0] 3
2 GND 4 2 GND 4
23 port0_p[1] 5 23 port1_p[1] 5
44 GND 6 44 GND 6
3 port0_n[1] 7 3 port1_n[1] 7
24 GND 8 24 GND 8
45 port0_p[2] 9 45 port1_p[2] 9
4 GND 10 4 GND 10
25 port0_n[2] 11 25 port1_n[2] 11
46 GND 12 46 GND 12
5 port0_p[3] 13 5 port1_p[3] 13
26 GND 14 26 GND 14
47 port0_n[3] 15 47 port1_n[3] 15
6 GND 16 6 GND 16
27 port0_p[4]
JP2
17 27 port1_p[4]
JP5
17
48 GND 18 48 GND 18
7 port0_n[4] 19 7 port1_n[4] 19
28 GND 20 28 GND 20
49 port0_p[5] 21 49 port1_p[5] 21
8 GND 22 8 GND 22
29 port0_n[5] 23 29 port1_n[5] 23
50 GND 24 50 GND 24
9 port0_p[6] 25 9 port1_p[6] 25
30 GND 26 30 GND 26
51 port0_n[6] 27 51 port1_n[6] 27
10 GND 28 10 GND 28
31 port0_p[7] 29 31 port1_p[7] 29
52 GND 30 52 GND 30
11 port0_n[7] 31 11 port1_n[7] 31
32 GND 32 32 GND 32
53 port0_p[8]
JP3
33 53 port1_p[8]
JP6
33
12 GND 34 12 GND 34
33 port0_n[8] 35 33 port1_n[8] 35
54 GND 36 54 GND 36
13 port0_p[9] 37 13 port1_p[9] 37
34 GND 38 34 GND 38
55 port0_n[9] 39 55 port1_n[9] 39
14 GND 40 14 GND 40
35 port0_p[10] 41 35 port1_p[10] 41
56 GND 42 56 GND 42
15 port0_n[10] 43 15 port1_n[10] 43