RTD Embedded Technologies, Inc.
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26
FPGA35S6 User’s Manual
6.1.4
R_PORT0_IN
(R
EAD
)
This is the input register for the port0. This reads the current value the I/O.
6.1.5
R_PORT0_OUT
(W
RITE
)
This is the output register for the port0. The value to be output, direction must be set to output.
6.1.6
R_PORT0_DIR
(W
RITE
)
This is the direction register for port0. Indicates the direction of each pin ‘0’ = input ‘1’ = output
6.1.7
R_PORT1_IN
(R
EAD
)
This is the input register for the port1. This reads the current value the I/O.
6.1.8
R_PORT1_OUT
(W
RITE
)
This is the output register for the port1. The value to be output, direction must be set to output.
6.1.9
R_PORT1_DIR
(R
EAD
/W
RITE
)
This is the direction register for port1. Indicates the direction of each pin ‘0’ = input ‘1’ = output
6.1.10
R_PORT2L_IN
(R
EAD
)
This is the input register for the port2 low, port2_[0]…port2_[15]. This reads the current value the I/O.
6.1.11
R_PORT2L_OUT
(W
RITE
)
This is the output register for the port2 low, port2_[0]…port2_[15]. The value to be output, direction must be set to output.
6.1.12
R_PORT2L_DIR
(R
EAD
/W
RITE
)
This is the direction register for port2 low, port2_[0]…port2_[15]. Indicates the direction of each pin ‘0’ = input ‘1’ = output
6.1.13
R_PORT2H_IN
(R
EAD
)
This is the input register for the port2 high, port2_[16]…port2_[19]. This reads the current value the I/O.
6.1.14
R_PORT2H_OUT
(W
RITE
)
This is the output register for the port2 high, port2_[16]…port2_[19]. The value to be output, direction must be set to output.
6.1.15
R_PORT2H_DIR
(R
EAD
/W
RITE
)
This is the direction register for port2 high, port2_[16]…port2_[19]. Indicates the direction of each pin ‘0’ = input ‘1’ = output
6.1.16
R_DDR_RD_DATA
(R
EAD
)
Reads the data of the DDR2 SRAM at R_DDR_ADDR location
A read is performed by writing address to R_DDR_ADDR.
6.1.17
R_DDR_WR_DATA
(R
EAD
/W
RITE
)
Writes data in registry to location R_DDR_ADDR of the DDR2 SRAM
6.1.18
R_DDR_ADDR
(R
EAD
/W
RITE
)
Address pointer of the DDR2 SRAM.
