RTD Embedded Technologies, Inc.
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iv
FPGA35S6 User’s Manual
Table of Contents
1
Introduction
7
1.1
Product Overview........................................................................................................................................................................ 7
1.2
Board Features ........................................................................................................................................................................... 7
1.3
Ordering Information ................................................................................................................................................................... 8
1.4
Contact Information .................................................................................................................................................................... 8
1.4.1
Sales Support
8
1.4.2
Technical Support
8
2
Specifications
9
2.1
Operating Conditions .................................................................................................................................................................. 9
2.2
Electrical Characteristics ............................................................................................................................................................ 9
3
Board Connection
10
3.1
Board Handling Precautions ..................................................................................................................................................... 10
3.2
Physical Characteristics ............................................................................................................................................................ 10
3.3
Connectors and Jumpers .......................................................................................................................................................... 11
3.3.1
External I/O Connectors
12
CN3: Xilinx JTAG Programming Header
12
CN8: High Speed Digital I/O Connector
13
CN4 & CN9: Digital I/O Connector
14
3.3.2
Bus Connectors
14
CN1 (Top) & CN2 (Bottom): PCIe Connector
14
3.3.3
Jumpers
14
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper
14
JP7: Reserved
15
3.3.1
Solder Jumper
15
B1: Pull up Voltage
15
B2: Pull up Voltage
15
3.4
Steps for Installing .................................................................................................................................................................... 16
4
IDAN Connections
17
4.1
Module Handling Precautions ................................................................................................................................................... 17
4.2
Physical Characteristics ............................................................................................................................................................ 17
4.3
Connectors and Jumpers .......................................................................................................................................................... 18
P2 & P3: Digital I/O Connector
18
P4: High Speed Digital I/O Connector
19
4.3.1
Bus Connectors
21
CN1 (Top) & CN2 (Bottom): PCIe Connector
21
4.3.2
Jumpers
21
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper
21
JP7: Reserved
21
4.3.3
Solder Jumper
21
B1: Pull up Voltage
21
B2: Pull up Voltage
21
4.4
Steps for Installing .................................................................................................................................................................... 22
5
Functional Description
23
5.2
Oscillator ................................................................................................................................................................................... 23
5.3
EEPROM .................................................................................................................................................................................. 23
5.4
DDR2 SRAM ............................................................................................................................................................................. 23
5.5
Digital I/O .................................................................................................................................................................................. 24
6
Register Address Space
25
