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20
FPGA35S6 User’s Manual
Table 12: P4 Pin Assignments
IDAN P4 Pin
Signal
C8 Pin
Row 1
Row 2
Row 3
9
Port2_p[10] 25
30
Port2_n[10] 26
51
Port2_p[11] 27
10
Port2_n[11] 28
31
GND
29
52
GND
30
11
Port2_p[12] 31
32
Port2_n[12] 32
53
Port2_p[13] 33
12
Port2_n[13] 34
33
Port2_p[14] 35
54
Port2_n[14] 36
13
Port2_p[15] 37
34
Port2_n[15] 38
55
GND
39
14
GND
40
35
Port2_p[16] 41
56
Port2_n[16] 42
15
Port2_p[17] 43
36
Port2_n[17] 44
57
Port2_p[18] 45
16
Port2_n[18] 46
37
Port2_p[19] 47
58
Port2_n[19] 48
17
+5V
49
38
GND
50
59
Reserved
18
Reserved
39
Reserved
60
Reserved
19
Reserved
40
Reserved
61
Reserved
20
Reserved
41
Reserved
62
Reserved
21
Reserved
42
Reserved