Ross HDC-8222A, User Manual

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HDC-8222A User Manual (Iss. 02) Introduction • 1–5
Overview
Starting in the upper left of the block diagrams, the dual-rate (HD/SD) serial digital signal is
equalized, re-clocked and then de-serialized. A re-clocked copy of the input is driven out of up to
four BNCs (number of BNCs is dependent on the rear module you are using). Once de-serialized,
the video standard and frame rate is determined.
Coming out of the de-serializer, the parallel video data path goes to the image scalar circuitry,
where it is down, aspect and/or frame rate converted depending on the signal input and user
settings. After conversion audio, timecode, and closed captioning signals are embedded. Finally
the reticule overlays (if any) are applied, and the signal passes through circuitry to reduce output
clock jitter.
Up to four copies of SD analog composite and SD-SDI are generated and sent to four, 2x1
switches (
S7 , S8 , S9 , and S10 ) that allow you to select analog composite or SDI for the outputs.
The HDC-8222A also has a special feature called Field Lock for 720p down-converts. The 720p
signals do not carry information indicating which frame should become a down-converted even
field and which should be a down-converted odd field. When Field Lock is enabled, the card uses
the frame reference as a guide to ensure that the down-converted odd/even sequence matches the
odd/even sequence of the reference.