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User’s Guide
BD96801-SPA7-EVK-301
© 2022 ROHM Co., Ltd.
65UG018E Rev.001
July 2022
3.10.
I2C interface
The test points TP132 to TP134 offer access to the I2C bus which may be needed to read out registers (e.g., status registers) of the
PMIC BD96801.
It is also useful to change settings of the PMIC BD96801 by programming the onboard EEPROM.
Attention: be careful when changing settings! This may lead to the destruction of the board if not applied carefully.
The default 7-bit slave address of the PMIC is 0x60. The default 7-bit slave address of the EEPROM is 0x50.
Note that I2C signals are related to the supply voltage of PMIC and EEPROM (5V).
See below the pin assignment of the I2C interface.
TP132: GND
TP133: SDA
TP134: SCL
Figure 9: I2C interface
4. Testing default FPGA software
For testing the default demo software of the board, follow the steps as described in the above section “Power-up”.
When USER2 switch (SW502) is in Low position, the core current toggles with a frequency of 500Hz between 660mA and 1.0A.
LED501 blinks with a frequency of around 0.5Hz. Switching USER2 switch (SW502) to High position keeps the core current at con-
stantly 0A. Also, LED501 stops blinking.
To measure the core voltage (1.0V) of the Spartan-7 FPGA, connect a voltage probe between TP20 (V_1.0) and TP21 (GND).
Figure 10: measure core voltage
Tip of voltage probe
GND of voltage probe
