6/36
© 2022 ROHM Co., Ltd.
65UG018E Rev.001
July 2022
User’s Guide
2. Introduction
Current FPGA-based designs require highly integrated power supply solutions containing multiple well-defined and accurate output
voltages. Starting up and shutting down an FPGA demands a well-defined power sequencing. The scalable PMIC BD96801 is a
configurable power management IC that can quickly be adapted to work with various FPGAs. The voltages of the PMIC outputs
are programmable via OTP setting or I2C. The timing for up- and down-sequencing of the voltage rails can be individually defined
as well.
This manual explains how to use the BD96801-SPA7-EVK-301 with ROHM’s PMIC BD96801 in UQFN48FV6060 package.
3. Key features
The evaluation board is an eight layered PCB with dimensions of approximately 120 mm by 100 mm. Figure 1 shows the picture of
the EVK, indicating key components onboard. To operate the EVK you need a DC/DC power supply (10V to 24V, > 300mA).
3.1. Spartan-7 EVK description
Figure 1: Evaluation board BD96801-SPA7-EVK-301
System switches
Oscillator
User switches
Primary buck
regulator BD9F500
Termination
Regulator
BD35395
PMIC BD96801
DDR3L 4Gb
NOR Flash memory 128
Mb
JTAG port
FPGA
Spartan-7 XC7S50
36 general pur-
pose I/Os
EEPROM 1kb
24V input power
supply connector
CN130:
STBY 1-2
ENABLE 3-4
I2C interface
