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User's Guide ADI-192 DD   © RME

33

 

10.7 Firmware 

 
The ADI-192 DD's main part has been realized using programmable logic. By exchanging a little 
component called EPROM, both function and behaviour of the unit can be changed at any time. 
 
At the time of writing this manual, the unit is shipped with firmware 2.2. The firmware version is 
displayed after power on by the SYNC and LEVEL LEDs of the INPUT MONITOR for about one 
second. 
 
Firmware 1.1: First firmware for the ADI-192 DD. 
 
The current firmware 2.2 includes no bug fixes. Therefore owners of an ADI-192 DD with earlier 
firmware will have to accept costs for an update to version 2.2. However these costs are limited 
to material and work time (EPROM, flashing the EPROM, shipping). 
 
 

Changes in firmware 1.2 

 
1. The three sections OUTPUT now have a fourth setting, OFF. In this state no LED is lit. The 
corresponding output provides an empty frame signal of the current sample rate. The option to 
switch off specific outputs provides an even better overview to the user interface of the ADI-192 
DD, as unused outputs no longer emit light signals. 
 
2. The SOURCE LEDs of the three OUTPUT sections no longer light up constantly, but depend-
ing on the LOCK state. So when selecting an input without present input signal, the correspond-
ing LED in the OUTPUT section flashes in the same way as the ones in the SRC and CLOCK 
SECTION. This change unifies the user interface of the ADI-192 DD and improves overview, 
because invalid inputs will be recognized in any part of the user interface immediately. 
 
3. The AES Sync display in the INPUT MONITOR section has been extended. In case multiple 
AES signals with different ranges (Single, Double or Quad) are attached simultaneously and are 
synchronous as well, flashing LEDs will indicate that these signals are still invalid for the cur-
rently chosen SRC mode. 
 
4. New function 

SRC Multi-range

. Keep the button SRC RANGE pressed and both LEDs DS 

and QS will light up. In INPUT MONITOR the LEDs DS and QS of the AES inputs will light up as 
well. With this the SRC signals that now any input signal is accepted. Single, Double and Quad 
Speed can be attached to the four AES inputs in any combination, and converted to any desired 
output frequency. In this mode neither Double nor Quad Wire are supported as input signal. 
 
Note: With firmware 1.2 the SRC LEDs of the OUTPUT sections have been changed from red 
to blue. Unfortunately the orange QS LEDs were nearly identical to the red SRC LEDs. The 
changed colour helps to notice an active SRC mode. 
 
 

Changes in firmware 2.2 

 
1. More sensitive mute for TDIF when encountering clock problems. Prevents noise in certain 
situations with invalid clock. (v 2.1) 
 
2. New function Follow Clock for automated CLOCK STATE switching. 

Summary of Contents for ADI-192 DD

Page 1: ...SyncAlign SyncCheck Intelligent Clock Control Hi Precision 24 Bit 192 kHz 8 Channel Triple Universal Format Converter 8 Channel Sample Rate Converter ADAT optical TDIF AES EBU Interface SteadyClock T...

Page 2: ...2 TDIF 21 7 3 ADAT Optical 22 8 The Sample Rate Converter 8 1 General 23 8 2 Operation 23 8 3 Clock Decoupling using the SRC 25 8 4 The SRC as Signal Conditioner 25 9 Word Clock 9 1 Word Clock Input a...

Page 3: ...ture and water from entering the device Never leave a pot with liquid on top of the device Do not use this product near water i e swimming pool bathtub or wet basement Danger of condensation inside do...

Page 4: ...4 User s Guide ADI 192 DD RME...

Page 5: ...User s Guide ADI 192 DD RME 5 User s Guide ADI 192 DD General...

Page 6: ...th chapter 11 1 Terminology 2 Package Contents Please check that your ADI 192 DD package contains each of the following ADI 192 DD User s Guide Power chord 3 Brief Description and Characteristics The...

Page 7: ...I O port via TOSLINK cable The rear of the ADI 192 DD provides all the connections eight AES EBU XLR four ADAT optical TOSLINK two TDIF D sub 25 three word clock BNC and mains power ADAT I O MAIN TOS...

Page 8: ...ined in the CLOCK SECTION The button CLOCK steps through the choices external clock AES TDIF ADAT and word and in ternal clock 44 1 or 48 kHz The button STATE defines the sample rate range for both in...

Page 9: ...and ADAT at the same time just an example Any combination that one can imagine is allowed The big block diagram also printed on the unit s cover see chapter 12 shows further details like the AES inpu...

Page 10: ...f business drawn up by Audio AG apply at all times 6 Appendix RME news and further information can be found on our website http www rme audio com Distributor Audio AG Am Pfanderling 60 D 85778 Haimhau...

Page 11: ...ser is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Conn...

Page 12: ...12 User s Guide ADI 192 DD RME...

Page 13: ...User s Guide ADI 192 DD RME 13 User s Guide ADI 192 DD Usage and Operation...

Page 14: ...ing will let the DW Double Wire LED light up Unfortunately this information is insufficiently standardised and is even set falsely from several devices Therefore the DW LED is just a user information...

Page 15: ...ces is synchronous to the ADI 192 DD Therefore the external device has to be syn chronized to the ADI 192 DD s word clock out or AES TDIF ADAT out The ADI 192 DD thus has to be master all devices conn...

Page 16: ...Hz 1 channel per AES wire The effective sample frequency is double the clock of the AES wire QW Quad Wire 2 channels 176 4 192 kHz 1 channel via 2 AES wires The effective sample frequency is four time...

Page 17: ...n but also with SRC activated The ADI 192 DD supports all currently known formats in the range of 32 kHz up to 192 kHz including sample multiplexing Single Wire 8 channels 32 kHz 192 kHz 2 channels pe...

Page 18: ...a b 3a b 4a b 5a b 6a b 7a b 8a b With input signals in the Quad Speed range the SRC RANGE or the Clock Section STATE have to be switched into QS mode manually depending on the current application Eac...

Page 19: ...UX Additional port for receiving channels 5 to 8 in S MUX or 3 and 4 in S MUX4 mode With input signals encoded as S MUX the SRC RANGE or the Clock Section STATE have to be switched into DS mode manual...

Page 20: ...in a channel status coding which is being used for transmitting further information The output signal coding of the ADI 192 DD has been implemented according to AES3 1992 Amendment 4 32 kHz 44 1 kHz 4...

Page 21: ...ons SW DW and QW are available The distribution of the samples performed in the Double Wire mode equals the S MUX method and is done as follows Channel Port L 1 R 1 L 2 R 2 L 3 R 3 L 4 R 4 Samples 1a...

Page 22: ...al MAIN carries the channels 1 to 4 in case of S MUX4 MAIN carries channels 1 and 2 ADAT AUX Additional port for a transmission of channels 5 to 8 in S MUX or 3 and 4 in S MUX4 mode When operating in...

Page 23: ...spectively Thus 192 kHz can be converted to any sample rate down to 32 kHz and 32 kHz can be converted to any fre quency up to 192 kHz When using the internal clock every SRC also works as a jitter ki...

Page 24: ...ll light up automatically and can t be deselected At 96 kHz only DS and QS can be selected since the audio signal can t be 48 kHz At 48 kHz however the device can not determine whether the signal is 4...

Page 25: ...ng synchronization Clicks and drop outs are the consequence Normally the mixing console works as master and delivers a reference signal word clock to all other devices But this is only possible if the...

Page 26: ...s constantly active providing the current sample frequency as word clock signal In master mode the word clock will be fixed to 44 1 kHz or 48 kHz DS x 2 QS x 4 In any other case the sample rate is ide...

Page 27: ...by 256 inside the device using a spe cial PLL to about 11 2 MHz This signal then replaces the one from the quartz crystal Big dis advantage because of the high multiplication factor the reconstructed...

Page 28: ...Ohms you have to take into account that a device of which the input only works from 2 8 Volts and above does not function correctly al ready after 3 meter cable length So it is not astonishing that be...

Page 29: ...User s Guide ADI 192 DD RME 29 User s Guide ADI 192 DD Technical Reference...

Page 30: ...4 2 x 8 channels 24 bit 48 kHz equalling 4 channels 24 bit 192 kHz Bitclock PLL ensures perfect synchronisation even in varispeed operation Lock range 28 kHz 54 kHz Jitter when synced to input signal...

Page 31: ...s 24 bit 48 kHz equalling 8 channels 24 bit 96 kHz S MUX4 2 x 8 channels 24 bit 48 kHz equalling 4 channels 24 bit 192 kHz TDIF 2 x D sub 25 pin according to TDIF 1 Standard 8 channels 24 bit up to 48...

Page 32: ...7 2 x 1 73 x 9 3 Weight 2 kg 4 4 lbs Temperature range 5 up to 50 Celsius 41 F up to 122 F Relative humidity 75 non condensing 10 6 Connector Pinouts D Sub TDIF 1 The 25 pin D sub connectors are wired...

Page 33: ...nd ing LED in the OUTPUT section flashes in the same way as the ones in the SRC and CLOCK SECTION This change unifies the user interface of the ADI 192 DD and improves overview because invalid inputs...

Page 34: ...requires two AES EBU ports See chapter 11 3 The Double Wire method is an industry standard today however it has a number of different names like Dual AES Double Wide Dual Line and Wide Wire The AES3 s...

Page 35: ...from internal clock to AES its internal clock will then be the clock delivered by the CD Player But in case a DAT recorder is connected as a second source there will again be a slight difference in th...

Page 36: ...g digital tape recorders But also other and newer interfaces like ADAT or TDIF are still using this technique And finally it can be used to transfer 192 kHz using 96 kHz capable equipment Since the AD...

Page 37: ...ce is described by IEC 60958 Type AES3 1992 IEC 60958 Connection XLR RCA Optical Mode Balanced Un balanced Impedance 110 Ohm 75 Ohm Level 0 2 V up to 5 Vss 0 2 V up to 0 5 Vss Clock accuracy not speci...

Page 38: ...to AES 5 AES to ADAT ADAT to AES 6 TDIF to TDIF 2 ADAT to ADAT 3 ADAT to TDIF TDIF to ADAT 5 ADAT to TDIF TDIF to AES AES to ADAT 8 AES to AES with SRC 144 Double Speed AES to AES 5 AES to TDIF TDIF t...

Page 39: ...z SteadyClock has originally been de veloped to gain a stable and clean clock from the heavily jittery MADI data signal The embedded MADI clock suffers from about 80 ns jitter caused by the time resol...

Page 40: ...40 User s Guide ADI 192 DD RME 12 Block Diagram...

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