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Renesas SH7262 Series, Hardware Design Manual

The Renesas SH7262 Series offers a comprehensive Hardware Design Manual for users to easily understand and implement this advanced technology. This valuable manual is available for free download at the mentioned website, providing users with all the necessary information and guidelines to optimize their product designs and maximize their potential.

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SH7262/SH7264 Group 

Hardware Design Guide 

REJ06B0999-0100  Rev. 1.00 

 

Page 5 of 36 

Jun. 30, 2010 

 

 

1.2 Bypass 

Capacitor 

A multilayer ceramic capacitor must be installed as a bypass capacitor for each pair of power supply pins. Install the 
bypass capacitor as close as possible to the LSI power supply pins. Connect the bypass capacitor with capacitance 
between 0.1 and 0.33 µF (recommended value). 

Figure 2 shows an example of installing an external capacitor with the SH7262. Figure 3 shows an example of installing 
an external capacitor with the SH7264. 

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PLQP0176KB-A

Top view

PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PVcc
PF1
Vss
PF0
Vcc
PE5
PE4
PE3
PE2
PE1
PE0
PVcc
Vss
PD15
PD14
PD13
PD12
PD11
PD10
Vss
PVcc
PD9
PD8
PD7
PD6
PD5
PD4
PD3
Vcc
PD2
Vss
PD1
PVcc
PD0
PC0
PC1

PC2

PC3

PC4

PC5

PC6

Vcc

PC7

Vss

PC8

PVcc

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Vcc

PB8

Vss

PB9

PVcc

PB10

PB11

PB12

PB13

PB14

PB15

Vcc

PB16

Vss

CKIO

PVcc

PB17

PB18

PB19

PB20

PB21

PB22

Vcc

Vss

PVcc

RES

NMI

Vcc

PF10

Vss

PF11

PVcc

PF12

AUDIO_X1

AUDIO_X2

PG0

PG1

Vcc

PG2

Vss

PG3

PVcc

PG4

PG5

PG6

PG7

PG8

PG9

PG10

Vcc

PG11

Vss

PG12

PVcc

PG13

PG14

PG15

PG16

PG17

PG18

PG19

PG20

Vcc

Vss

PVcc

TCK

TMS

TDI

TDO

ASEBRKAK

/

ASEBRK

TRST

AVcc

AVref

AVss

PH3
PH2
PH1
PH0

USBUVss
USBUVcc

USBAVss
USBAVcc

USBAPVss
USBAPVcc

REFRIN

USBDVss
USBDVcc

VBUS

DP

DM

USBDPVss
USBDPVcc

ASEMD

USB_X2
USB_X1

PVcc

PJ0

Vss

PJ1

Vcc

PJ2
PJ3

Vss

RTC_X2
RTC_X1

PVcc

Vss

PA0
PA1

XTAL

EXTAL

PA2

PLLVss

PA3

PLLVcc

 

Figure 2 Installing an External Capacitor with the SH7262 

Summary of Contents for SH7262 Series

Page 1: ...10 4 Operating Mode Control 12 5 External ROM 17 6 Handling of Pins 21 7 On chip Resource Access 26 8 Endianness 27 9 Power down Modes 28 10 References 34 Related Application Notes For more information refer to the following application notes SH7262 SH7264 Group Guidelines for Hi Speed USB 2 0 Board Design SH7262 SH7264 Group Using Deep Standby Mode in Power down Mode SH7262 SH7264 Group Connectin...

Page 2: ...pply 0 V The system does not work when any of those pins are open PVcc I O circuit power supply 3 0 to 3 6 V Power supply pin for I O pins Connect all PVcc pins to the system power supply The system does not work when any of those pins are open USBDPVcc 2 Transceiver digital pin power supply 3 0 to 3 6 V Power supply for USB pins USBDPVss 3 Transceiver digital pin ground 0 V Ground for USB pins US...

Page 3: ...7 Analog reference voltage 3 0 to 3 6 V A D Converter reference voltage pin Notes 1 USBAVcc USBDVcc and USBUVcc must be at the same electric potential as the Vcc 2 USBAPVcc and USBDPVcc must be at the same electric potential as the PVcc 3 USBAVss USBDVss USBUVss USBAPVss and USBDPVss must be at the same electric potential as the Vss 4 Isolate analog power supplies USBAVcc USBAVss USBAPVcc and USBA...

Page 4: ...as short as possible and pattern width must be as wide as possible to reduce inductive interferences Since the analog power supply pins of the PLL are sensitive to the noise the system may mulfunction due to inductive interference at the other power supply pins To prevent such malfunction do not supply the same resources to the analog power supply pins and the digital power supply pins Vcc and PVc...

Page 5: ... 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 PLQP0176KB A Top view PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PVcc PF1 Vss PF0 Vcc PE5 PE4 PE3 PE2 PE1 PE0 PVcc Vss PD15 PD14 PD13 PD12 PD11 PD10 Vss PVcc PD9 PD8 PD7 PD6 PD5 PD4 PD3 Vcc PD2 Vss PD1 PVc...

Page 6: ...9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PVcc PF1 Vss PF0 Vcc PK7 PK6 PK5 PK4 PE5 PE4 PE3 PE2 PE1 PE0 PK3 PVcc Vss PK2 PK1 PK0 PD15 PD14 PD13 PD12 PD11 PD10 Vss PVcc PD9 PD8 PD7 PD6 PD5 PD4 PD3 Vcc PD2 Vss PD1 PVcc PD0 PC0 PC1 PC2 PC3 Vss PC4 PVcc PC9 PC10 PC5 PC6 Vcc PC7 Vss PC8 PVcc PB1 PB2 PB3 PB4 PB5 PB6 PB7 Vcc PB8 Vss PB9 PVcc PB10 PB11 PB12 PB13 PB14 PB15 Vcc PB16 Vss CKIO PVcc PB17 PB18 PB19 PB20 PB2...

Page 7: ... low level during the oscillation settling time at power on or when exiting from software standby mode and deep standby mode Keep the RES pin at low level for at least 20 tcyc when setting the RES pin to low level while the clock is running The power on oscillation settling time tosc1 is 10 ms which is specified from when the Vcc exceeds the minimum operating voltage until the RES pin exceeds the ...

Page 8: ...ts power on reset exception handling however the Watchdog reset control status register WRCSR of the WDT and the Frequency control register FRQCR of the Clock Pulse Generator CPG are not initialized note Note For more information on register status refer to 36 3 Register States in Each Operating Mode in the SH7262 Group SH7264 Group Hardware Manual 2 4 Manual Reset This section describes sources f...

Page 9: ...SH7262 SH7264 Group Hardware Design Guide REJ06B0999 0100 Rev 1 00 Page 9 of 36 Jun 30 2010 RES WDTOVF Reset input Low active Reset signal to entire system Low active Figure 5 System Reset using WDTOVF ...

Page 10: ...er is in high speed 48 MHz 100 ppm When the USB controller is NOT in high speed and operating as the USB host 48 MHz 500 ppm When the USB controller is NOT in high speed and operating as the USB function 48 MHz 2500 ppm AUDIO_X1 AUDIO_X2 When connecting a crystal resonator 10 MHz to 25 MHz When inputting an external clock 1 MHz to 25 MHz RTC_X1 RTC_X2 32 768 kHz 3 2 Connecting an External Clock Fi...

Page 11: ...wn in Figure 7 and evaluate the entire system before using As the circuit ratings of the crystal resonator vary with the resonator and the floating capacitance it is recommended to consult the crystal resonator manufacturer on the constants Make sure that the applied voltage to the clock pin does not exceed the maximum rating The SH7264 includes the feedback resistor however an external feedback r...

Page 12: ...o the Renesas Serial Peripheral Interface channel 0 at low speed Boot mode 3 4 1 2 Boot Mode 0 Boot mode 0 allows the engineer to boot the SH7264 from memory which is connected to CS0 space This section describes the steps initiated by the MCU in boot mode 0 note 1 Retrieve the execution start address from the exception handling vector table After waking up from power on reset CPU retrieves the in...

Page 13: ...mory connected to RSPI channel 0 to the start address of high speed internal RAM In boot mode 1 the communication speed is at the 1 2 of the bus clock Bφ In boot mode 3 the communication speed is at the 1 4 of the bus clock Bφ Set the boot mode according to the specifications of the serial flash memory used After transferring the loader program is completed CPU jumps to high speed internal RAM to ...

Page 14: ... address of high speed internal RAM as the following steps It searches the loader program in NAND flash memory transfers the loader program to the high speed internal RAM and jumps to the entry function of the loader program a Searches for loader program store blocks block address 0 to 1023 maximum b Reads the 8 KB loader program 16 sectors transfers the loader program to the high speed internal R...

Page 15: ...umption 4 2 3 Mode 1 Mode 1 provides the clock from the USB_X1 pin or a crystal resonator PLL circuit shapes the waveform sets the Frequency control register FRQCR to multiply the frequency and supplies the clock to the SH7264 The CKIO frequency range is USB_X1 crystal 48 MHz To reduce the power consumption fix the EXTAL pin connect to pull up or pull down resistors connect to the power supply or ...

Page 16: ...N 8 8 4 2 10 to 18 40 to 72 80 to 144 40 to 72 20 to 36 H x004 ON 8 8 4 4 3 10 to 18 40 to 72 80 to 144 40 to 72 13 3 to 24 H x005 ON 8 8 4 1 10 to 18 40 to 72 80 to 144 40 to 72 10 to 18 H x006 ON 8 8 4 2 3 10 to 18 40 to 72 80 to 144 40 to 72 6 7 to 12 H x013 ON 8 4 4 2 10 to 18 40 to 72 40 to 72 40 to 72 20 to 36 H x014 ON 8 4 4 4 3 10 to 18 40 to 72 40 to 72 40 to 72 13 3 to 24 H x015 ON 8 4 4...

Page 17: ...d MD_BOOT1 pins to low level boot mode 0 5 1 2 NOR Boot Mode BSC Initial State In Boot Mode 0 NOR Boot the Bus State Controller must be programmed to operate with NOR FLASH To provide maximum flexibility in the engineers design the minimal configuration is performed as follows A1 A20 active D0 D15 as data bus RD and CS0 active Engineers implementing large NOR FLASH using address lines above A20 mu...

Page 18: ...the external device does not malfunction when the MCU pins are in the high impedance state SSL00 pin is pulled up by the external resistor to high level Pull up or down the RSPCK0 and MOSI0 pins As the MISO0 pin is an input pin pull up or down it to avoid floating to an invalid logic level Table 7 Multiplexed Pins SH7264 Port Control Register Peripheral Functions Pin Name Register Name MD Bit Sett...

Page 19: ...4 3 3 V 3 3 V 3 3 V 8 bit RE WE 3 3 V 3 3 V FRE FWE R B CLE ALE FCLE FALE Figure 12 Typical NAND Flash Memory Circuit Note Pull up or pull down the control signal pins using external resistors Pull up or pull down the control signal pins so the external device does not malfunction when the MCU pins are in the high impedance state FCE FRE and FWE pins are pulled up by the external resistor to high ...

Page 20: ...PWM2C PD9 D9 NAF1 PWM2B PD8 D8 NAF0 PWM2A FWE 1 PDCR1 PD7MD 1 0 B 01 PD7 D7 FWE PWM1H FALE 1 PDCR1 PD6MD 1 0 B 01 PD6 D6 FALE PWM1G FCLE 1 PDCR1 PD5MD 1 0 B 01 PD5 D5 FCLE PWM1F FRE 1 PDCR1 PD4MD 1 0 B 01 PD4 D4 FRE PWM1E FCE PFCR2 PF10MD 2 0 B 101 PF10 A24 SSIWS3 SSL00 TIOC3B FCE NAND Flash Memory Controller FRB PFCR2 PF9MD 2 0 B 101 PF9 A23 SSISCK3 RSPCK0 TIOC3A FRB Note 1 Bus State Controller p...

Page 21: ...mended connections as shown in Figure 13 and Figure 14 are used 6 2 TRST Pin The TRST pin is an initialization signal input pin in user debugging interface H UDI It accepts inputs from the H UDI serial data I O clock pin TCK asynchronously to reset the H UDI at low level The TRST should have a 1K pull down as shown in Figure 13 and Figure 14 for correct operation whether using or not using the emu...

Page 22: ...GND GND GND 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 2 4 6 8 12 10 14 16 18 20 22 24 26 28 30 32 34 36 AUDATA0 AUDATA2 AUDATA1 AUDATA3 TCK RES TMS TDO TDI TRST ASEBRKAK ASEBRK AUDCK AUDSYNC AUDCK N C PVcc ASEMD PVcc PVcc 1 kΩ Reset signal All pins must be pulled up by resistors with 4 7 kΩ or greater User system PVcc I O power supply 36 pin H UDI port connector 1 kΩ Figure 13 Recommended Cir...

Page 23: ...7 are input only applicable when using as multiplexed PH0 to PH7 ports Place the digital circuit and analog circuit as far apart as possible on the board i e maintain some isolation between the high speed digital and analog signals Analog circuits signals must be wired prior to digital circuit signals and avoid intersecting with or being close to the digital circuit signals to avoid coupling Failu...

Page 24: ...tee the conversion accuracy for the input signal when its source impedance is equal to or less than 5 kΩ This specification is to charge the input capacitance of the A D Converter ADC sample and hold circuit within the sampling time When the sensor output impedance exceeds 5 kΩ charging may be insufficient and it may not be possible to guarantee A D conversion accuracy If a large capacitance is pr...

Page 25: ... power supply or ground Other I O only pins Set to input pin and fix the level pull up or pull down Or set to the output pin and open Output only pins Leave open ASEMD Fix to high level pull up or connect to the power supply TRST Fix to low level pull down or connect to ground TCK TMS TDI Fix the level pull up pull down connect to the power supply or ground TDO ASEBRKAK ASEBRK Leave open Note We r...

Page 26: ... clock ratio Number of cycles to access Large capacity internal RAM 1 Internal peripheral register 1 1 3 Bφ 2 1 2 Bφ 3 1 2 Bφ 4 1 2 Bφ 6 1 1 Bφ Read 1 Iφ 1 Iφ 8 1 1 Bφ 1 Bφ 2 or more Pφ 1 1 2 Bφ 2 1 2 Bφ 3 1 2 Bφ 4 1 2 Bφ 6 1 1 Bφ Write 1 Iφ 1 Iφ 8 1 1 Bφ 1 Bφ 2 or more Pφ Note The High speed internal RAM and large capacity internal RAM are composed of several pages and each page has a port for re...

Page 27: ...e signals corresponding to addresses depend on the byte order big endian or little endian WE1 indicates address 0 in big endian but WE0 indicates address 0 in little endian IMPORTANT Since the instruction fetch is mixed with the 32 and 16 bit access code cannot be allocated to the little endian area Always execute instructions from the big endian areas internal or external NOTE Since the SH2A is n...

Page 28: ...o wake up the MCU 4 Module standby mode Set the MSTP bits in the STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 STBCR7 STBCR8 ON ON States held ON ON Specified module is OFF OFF ON Auto refresh Clear the MSTP bit to 0 Power on reset Only for H UDI and DMAC Notes 1 Pin state is either states held or high impedance 2 The Realtime Clock is ON when the START bit in the RCR2 register is 1 When waking up the MCU fr...

Page 29: ...y mode stops the SH7264 completely and turns OFF the SH7264 When executing the SLEEP instruction while the bits STBY and DEEP in STBCR1 is 1 the SH7264 transitions from the program execution state to deep standby mode Not only the CPU clock and on chip peripheral modules stop operation but all modules are off other than the data retention internal RAM which is set by bits RRAMKP3 to RRAMKP0 in the...

Page 30: ... 3 Pin States in Software Standby Mode and Deep Standby Mode The pin states in software standby mode and deep standby mode depend on the pin function or its setting Table 13 to Table 15 list pin states in software standby mode and deep standby mode Table 13 Pin States in Software Standby Mode and Deep Standby Mode 1 3 Pin Name Description CKIO Specified by CKOEN 1 0 bits FRQCR register Setting Sof...

Page 31: ...o PG0 PJ11 to PJ0 PK11 to PK0 PWM1A to PWM1H PWM2A to PWM2H Specified by the HIZ bit STBCR3 register 1 High impedance state 0 Pin state is retained for output pin and I O pin which is configured as output pin Pin state is in high impedance for I O pin which is configured as input pin Note When the AUDIO_XOUT pin state is retained it outputs either high level or low level signal and does not oscill...

Page 32: ... TCLKD AN7 to AN0 ADTRG FRB USB_X1 LCD_EXTCLK DV_CLK DV_DATA7 to DV_DATA0 DV_VSYNC DV_HSYNC SD_CD SD_WP High impedance state RxD7 to RxD0 SSIRxD0 SIOFRxD High impedance state RES ASEMD NMI VBUS REFRIN Input state RTC_X1 Specified by the RTCEN bit RCR2 register 1 Input state RTC_X1 is operating 0 High impedance state RTC_X1 is stopped Input pins IRQ7 to IRQ0 IERxD CRx1 CRx0 Software standby mode In...

Page 33: ...er when the EBUSKEEPE bit is set to 0 external memory control pin states are released immediately after waking up the MCU from deep standby mode Table 16 lists external memory control pins to enable the EBUSKEEPE bit setting Table 16 External Memory Control Pins to Enable the EBUSKEEPE Bit Setting Boot Mode 0 CS0 Space Boot Mode 2 NAND Flash Memory Boot Modes 1 and 3 Serial Flash Memory A20 to A1 ...

Page 34: ...sas Electronics website Hardware Manual SH7262 Group SH7264 Group Hardware Manual Rev 2 00 The latest version of the hardware manual can be downloaded from Renesas Electronics website Emulator Manual SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7264 SH7262 SH7266 and SH7267 The latest version of the emulator manual can be downloaded...

Page 35: ... REJ06B0999 0100 Rev 1 00 Page 35 of 36 Jun 30 2010 Website and Support Renesas Technology Website http www renesas com Inquiries http www renesas com inquiry All trademarks and registered trademarks are the property of their respective owners ...

Page 36: ...SH7262 SH7264 Group Hardware Design Guide REJ06B0999 0100 Rev 1 00 Page 36 of 36 Jun 30 2010 Revision Record Description Rev Date Page Summary 1 00 Jun 30 10 First edition issued ...

Page 37: ...s supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provi...

Page 38: ...rtificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life 8 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement...

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