SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 18 of 36
Jun. 30, 2010
5.2
Serial Flash Memory
Connect the serial flash memory to the SH7264 internal Renesas Peripheral Interface (RSPI). Figure 11 shows an
example of serial flash memory circuit. Set the SH7264 pin functions as shown in Table 7.
For more information, refer to the application note "SH7262/SH7264 Group Interfacing Serial Flash Memory Using the
Renesas Serial Peripheral Interface".
Serial Flash Memory
AT26DF161A
2 MB
SH7264
RSPCK0
SCK (Serial Clock)
SI (Serial Data Input)
SSL00
WP# (Write Protect)
DIP
Switches
3.3 V
CS# (Chip Select)
SO (Serial Data Output)
HOLD#
3.3 V
3.3 V
MOSI0
MISO0
3.3 V
3.3 V
3.3 V
Figure 11 Typical Serial Flash Memory Circuit
Note: Pull up or pull down the control signal pins using external resistors.
Pull up or pull down the control signal pins, so the external device does not malfunction when the MCU pins are
in the high impedance state. SSL00 pin is pulled up by the external resistor to high level. Pull up or down the
RSPCK0 and MOSI0 pins. As the MISO0 pin is an input pin, pull up or down it to avoid floating to an invalid
logic level..
Table 7 Multiplexed Pins
SH7264
Port Control Register
Peripheral
Functions
Pin Name
Register
Name
MD Bit Setting
SH7264
Multiplexed Pin Name
RSPI
MISO0
PFCR3
PF12MD[2:0] = B'011 PF12/BS#/MISO0/TIOC3D/SPDIF_OUT
MOSI0
PFCR2
PF11MD[2:0] = B'011
PF11/A25/SSIDATA3/MOSI0/TIOC3C/SPDIF_IN
SSL00
PFCR2
PF10MD[2:0] = B'011
PF10/A24/SSIWS3/SSL00/TIOC3B/FCE#
RSPCK0
PFCR2
PF9MD[2:0]
=
B'011
PF9/A23/SSISCK3/RSPCK0/TIOC3A/FRB
Note: SH7264 Multiplexed Pins
MISO0, MOSI0, SSL00, and RSPCK0 pins are multiplexed, and set to general-purpose I/O ports as default.
Before accessing serial flash memory, use the general-purpose I/O port control register to set the multiplexed
pins to RSPI pins. In SPI Boot mode, these pins are programmed by the loader on power up (refer to SPI boot
mode operation).
