SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 30 of 36
Jun. 30, 2010
9.5
Pin States in Power-down Modes
9.5.1
Pin States in Sleep Mode
As the peripheral modules operate in sleep mode, the pin state varies according to the operation of peripheral modules.
9.5.2
Pin States in Module Standby Mode
When using module standby function for the module specified as general-purpose I/O port, the pins of the module
whose registers to be initialized at the module standby function is configured to default state. The pin of the module
whose registers not to be initialized at the module standby function retains the state immediately before entering module
standby mode.
9.5.3
Pin States in Software Standby Mode and Deep Standby Mode
The pin states in software standby mode and deep standby mode depend on the pin function or its setting. Table 13 to
Table 15 list pin states in software standby mode and deep standby mode.
Table 13 Pin States in Software Standby Mode and Deep Standby Mode (1/3)
Pin Name
Description
CKIO
Specified by CKOEN [1:0] bits (FRQCR register)
Setting
Software standby
mode
Deep standby
mode
B'00
Hi-Z
Low or high level
B'01
Low level
Low or high level
B'10
Unstable clock
output
Low or high level
B'11 Hi-Z
Hi-Z
A25 to A0, CS6# to CS0#,
CE1A#, CE1B#, CE2A#, CE2B#,
RD#, RD/WR#, BS#,
ICIOWR#/AH#, ICIORD#,
WE1#/DQMLU/WE#,
WE0#/DQMLL
Specified by the HIZMEM bit (CMNCR register)
1: Output state
0: High impedance state
RAS#, CAS#, CKE
Specified by the HIZCNT bit (CMNCR register)
1: Output state
0: High impedance state
External
bus pins
D15 to D0, WAIT#, IOIS16#
High impedance state
