Renesas SH7262 Series, Hardware Design Manual

Page: 16 / 38

SH7262/SH7264 Group Hardware Design Guide
REJ06B0999-0100 Rev. 1.00 Page 16 of 36
Jun. 30, 2010
4.2.6 Available Clock Frequency Range
Table 6 lists clock operating modes and available clock frequency range; do not set these pins other than the
combinations shown in the table below.
Table 6 Relationship between Clock Operating Mode and Clock Frequency Range
PLL
Multiplier Available Clock Frequency Range (MHz) Clock
Operating
Mode FRQCR
Setting
(1)
PLL
Circuit
Ratio of
Internal
Clock
Frequencies
(I:B:P)
(2)
Input
Clock
(3)
Output
Clock
(CKIO pin)
Internal
Clock (I
φ
)
Bus Clock
(B
φ
)
Peripheral
Clock (P
φ
)
H'x104 ON (×12) 12:4:2 10 to 12 40 to 48 120 to 144 40 to 48 20 to 24
H'x106 ON (×12) 12:4:1 10 to 12 40 to 48 120 to 144 40 to 48 10 to 12
H'x124 ON (×12) 4:4:2 10 to 12 40 to 48 40 to 48 40 to 48 20 to 24
0
H'x126 ON (×12) 4:4:1 10 to 12 40 to 48 40 to 48 40 to 48 10 to 12
H'x104 ON (×12) 3:1:1/2 48 48 144 48 24
H'x106 ON (×12) 3:1:1/4 48 48 144 48 12
H'x124 ON (×12) 1:1:1/2 48 48 48 48 24
1
H'x126 ON (×12) 1:1:1/4 48 48 48 48 12
H'x003 ON (×8) 8:4:2 10 to 18 40 to 72 80 to 144 40 to 72 20 to 36
H'x004 ON (×8) 8:4:4/3 10 to 18 40 to 72 80 to 144 40 to 72 13.3 to 24
H'x005 ON (×8) 8:4:1 10 to 18 40 to 72 80 to 144 40 to 72 10 to 18
H'x006 ON (×8) 8:4:2/3 10 to 18 40 to 72 80 to 144 40 to 72 6.7 to 12
H'x013 ON (×8) 4:4:2 10 to 18 40 to 72 40 to 72 40 to 72 20 to 36
H'x014 ON (×8) 4:4:4/3 10 to 18 40 to 72 40 to 72 40 to 72 13.3 to 24
H'x015 ON (×8) 4:4:1 10 to 18 40 to 72 40 to 72 40 to 72 10 to 18
2
H'x016 ON (×8) 4:4:2/3 10 to 18 40 to 72 40 to 72 40 to 72 6.7 to 12
H'x003 ON (×8) 8/3:4/3:2/3 48 64 128 64 32
H'x004 ON (×8) 8/3:4/3:4/9 48 64 128 64 21.3
H'x005 ON (×8) 8/3:4/3:1/3 48 64 128 64 16
H'x006 ON (×8) 8/3:4/3:2/9 48 64 128 64 10.7
H'x013 ON (×8) 4/3:4/3:2/3 48 64 64 64 32
H'x014 ON (×8) 4/3:4/3:4/9 48 64 64 64 21.3
H'x015 ON (×8) 4/3:4/3:1/3 48 64 64 64 16
3
H'x016 ON (×8) 4/3:4/3:2/9 48 64 64 64 10.7
Notes: 1. "x" in the FRQCR setting depends on the setting in bits 12, 13, and 15.
2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
3. These values are the clock frequencies of the EXTAL pin input or a crystal resonator in modes 0
and 2.
In modes 1 and 3, these values are the clock frequencies of the USB_X1 pin input or a crystal
resonator.