Renesas R8C/Tiny Series, Software Manual, Page: 44 / 297

27
Chapter 2 Addressing Modes
20-bit absolute
abs20
abs20
dsp:20[A0]
dsp:20[A1]
Address register relative with
20-bit displacement
address A0
LDE, STE instructions
JMPI, JSRI instructions
PC
address
Register
A0 / A1
dsp
dsp
32-bit address register indirect
address
A0
A1
address-L
b16 b15 b0
b31
address-H
[A1A0]
The address indicated by 32 concat-
enated bits of address registers (A0
and A1) constitutes the effective
address to be operated on.
However, if the concatenated register
value exceeds FFFFF
16
, the bits
above bit 21 are ignored.
This addressing can be used in LDE
and STE instructions.
Memory
Memory
Memory
Memory
Register
Register
2.4 Special Instruction Addressing
The value indicated by abs20 constitutes
the effective address to be operated on.
The effective address range is 00000
16
to
FFFFF
16
.
This addressing can be used in LDE, STE,
JSR, and JMP instructions.
The address indicated by displacement
(dsp) plus the content of address register
(A0/A1)—added not including the sign
bits—constitutes the effective address to
be operated on.
However, if the addition resulted in exceed-
ing FFFFF
16
, the bits above bit 21 are
ignored, and the address returns to
00000
16
.
This addressing can be used in LDE, STE,
JMPI, and JSRI instructions.
The following lists the addressing mode and
instruction combinations that can be used.
dsp:20[A0]
LDE, STE, JMPI, and JSRI in-
structions
dsp:20[A1]
JMPI and JSRI instructions
2.4 Special Instruction Addressing