Renesas R8C/Tiny Series, Software Manual, Page: 276 / 297

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Chapter 5 Interrupt
5.7 Precautions for Interrupts
5.7 Precautions for Interrupts
5.7.1 Reading Address 00000
16
Avoid reading the address 00000
16
in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address
00000
16
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
If the address 00000
16
is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to “0”. This may cause a problem that the interrupt is canceled, or an
unexpected interrupt is generated.
5.7.2 SP Setting
Set any value in the SP before accepting an interrupt. The SP is set to “0000
16
” after reset. Therefore, if
an interrupt is accepted before setting any value in the SP, the program may go out of control.
5.7.3 Changing Interrupt Control Register
(1) Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to
occur, disable the interrupts before changing the interrupt control register.
(2) To modify any interrupt control register after disabling interrupts, be careful with the instructions
used.
When Changing Other Than IR Bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to “1” (interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
When Changing IR Bit
Even when the IR bit is cleared to “0” (interrupt not requested), it may not actually be cleared to “0”
depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to “0”.
(3) When disabling interrupts using the I flag, set the I flag according to the following sample programs.
Refer to #2 for the change of interrupt control registers in the sample programs.
Sample programs 1 to 3 are to prevent the I flag from being set to “1” (interrupt enabled) before writing
to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.