Renesas R8C/Tiny Series, Software Manual, Page: 273 / 297

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Chapter 5 Interrupt
5.5 Interrupt Priority
When two or more interrupt requests occur while 1 instruction is executed, whichever interrupt request is
acknowledged that has the highest priority.
The priority level of maskable interrupts (Peripheral function) can be selected arbitrarily by setting the
ILVL2 to ILVL0 bits. If some maskable interrupts are assigned the same priority level, the priority between
these interrupts is resolved by the priority that is set in hardware.
Special interrupts such as the watchdog timer interrupt have their priority levels set in hardware. Figure
5.5.1 lists the interrupt priority levels of hardware interrupts.
Software interrupts are not subjected to interrupt priority. They always causes control to branch to an
interrupt routine when the relevant instruction is executed.
5.5 Interrupt Priority
Figure 5.5.1 Interrupt priority levels of hardware interrupts
Reset
Watchdog timer
Oscillation stop detection
Peripheral function
Single step
Address match
High
Low