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23

Chapter 2  Addressing Modes

2.2  Guide to This Chapter

The following shows how to read this chapter using an actual example.

Address register relative

dsp:8[A0]

dsp:8[A1]

dsp:16[A0]

dsp:16[A1]

 Memory

A0 / A1

 

Register

address

dsp

(1)  Name

Indicates the name of addressing.

(2)  Symbol

Represents the addressing mode.

(3)  Explanation

Describes the addressing operation and the effective address range.

(4)  Operation diagram

Diagrammatically explains the addressing operation.

(2)

(1)

(3)

(4)

2.2  Guide to This Chapter

The value indicated by displacement
(dsp) plus the content of address
register (A0/A1)—added not includ-
ing the sign bits—constitutes the
effective address to be operated on.

However, if the addition resulted in
exceeding 0FFFF

16

, the bits above

bit 17 are ignored, and the address
returns to 00000

16

.

Summary of Contents for R8C/Tiny Series

Page 1: ...ICROCOMPUTER R8C Tiny Series 16 Rev 1 00 Revision date Jun 19 2003 Software Manual www renesas com Before using this material please visit our website to confirm that this is the most current document...

Page 2: ...here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors...

Page 3: ...dressing mode Chapter 2 Addressing Modes To understand instruction functions Syntax operation function selectable src dest label flag changes description example related instructions Chapter 3 Functio...

Page 4: ...eristics Hardware Manual Hardware specifications pin assignment memory map specifica tions of peripheral functions electrical characteristics timing chart Software Manual Detailed description about op...

Page 5: ...stack pointer ISP 5 1 3 7 Static base register SB 5 1 3 8 Flag register FLG 5 1 4 Flag Register FLG 6 1 4 1 Bit 0 Carry flag C flag 6 1 4 2 Bit 1 Debug flag D flag 6 1 4 3 Bit 2 Zero flag Z flag 6 1...

Page 6: ...instruction addressing 22 2 1 3 Bit instruction addressing 22 2 2 Guide to This Chapter 23 2 3 General Instruction Addressing 24 2 4 Special Instruction Addressing 27 2 5 Bit Instruction Addressing 30...

Page 7: ...PL When Interrupt Request Acknowledged 253 5 3 3 Saving Registers 254 5 4 Return from Interrupt Routine 255 5 5 Interrupt Priority 256 5 6 Multiple Interrupts 257 5 7 Precautions for Interrupts 259 5...

Page 8: ...6 157 157 158 159 160 160 161 165 167 169 170 ABS 39 ADC 40 ADCF 41 ADD 42 ADJNZ 44 AND 45 BAND 47 BCLR 48 BMCnd 49 BMEQ Z 49 BMGE 49 BMGEU C 49 BMGT 49 BMGTU 49 BMLE 49 BMLEU 49 BMLT 49 BMLTU NC 49 B...

Page 9: ...9 241 241 242 243 ROT 112 RTS 113 SBB 114 SBJNZ 115 SHA 116 SHL 117 SMOVB 118 SMOVF 119 SSTR 120 STC 121 STCTX 122 STE 123 STNZ 124 STZ 125 STZX 126 SUB 127 TST 129 UND 130 WAIT 131 XCHG 132 XOR 133 M...

Page 10: ...152 BNAND Logically AND inverted bits 50 153 BNOR Logically OR inverted bits 51 154 BNOT Invert bit 52 154 BNTST Test inverted bit 53 155 BNXOR Exclusive OR inverted bits 54 156 BOR Logically OR bits...

Page 11: ...Z Subtract conditional jump 115 224 JCnd Jump on condition 80 182 JMP Unconditional jump 81 184 JMPI Jump indirect 82 185 JSR Subroutine call 83 187 JSRI Indirect subroutine call 84 188 RTS Return fro...

Page 12: ...SHC Save control register 106 216 REIT Return from interrupt 108 216 STC Transfer from control register 121 232 STCTX Save context 122 233 UND Interrupt for undefined instruction 130 241 WAIT Wait 131...

Page 13: ...truction addressing 1 Has special instruction addressing 2 Only R1L can be selected 3 Only R0L can be selected 4 Only R0H can be selected ABS ADC ADCF ADD 1 ADJNZ 1 AND CMP DADC DADD DEC DIV DIVU DIVX...

Page 14: ...dsp 16 SB abs16 IMM8 IMM16 IMM20 IMM See page for function See page for instruction code number of cycles Addressing Mnemonic Quick Reference by Addressing general instruction addressing 1 Has specia...

Page 15: ...SB FB dsp 16 An dsp 16 SB abs16 IMM8 IMM16 IMM20 IMM STZX SUB TST XCHG XOR See page for function See page for instruction code number of cycles Addressing Mnemonic Quick Reference by Addressing gener...

Page 16: ...NTBH PC Addressing Mnemonic Quick Reference by Addressing special instruction addressing See page for function See page for instruction code number of cycles 1 Has general instruction addressing 2 INT...

Page 17: ...ase 8 SB FB base 16 An bit base 16 SB bit base 16 bit base 11 U I O B S Z D C Addressing Mnemonic Quick Reference by Addressing bit instruction addressing See page for function See page for instructio...

Page 18: ...ures of R8C Tiny series 1 2 Address Space 1 3 Register Configuration 1 4 Flag Register FLG 1 5 Register Bank 1 6 Internal State after Reset is Cleared 1 7 Data Types 1 8 Data Arrangement 1 9 Instructi...

Page 19: ...utation 1 1 1 Features of R8C Tiny series Register configuration Data registers Four 16 bit registers of which two registers can be used as 8 bit registers Address registers Two 16 bit registers Base...

Page 20: ...series the SFR area extends from 002FF16 toward lower addresses Addresses from 0040016 on make up a memory area In individual models of the R8C Tiny series a RAM area extends from address 0040016 tow...

Page 21: ...R2R0 or R3R1 Figure 1 3 1 CPU register configuration R0H High order of R0 b15 b8 b7 b0 R3 Data register Note Address register Note Frame base register Note Program counter Interrupt table register Us...

Page 22: ...t 1 3 5 Interrupt table register INTB The interrupt table register INTB consists of 20 bits indicating the initial address of an interrupt vector table 1 3 6 User stack pointer USP and interrupt stack...

Page 23: ...a negative value otherwise this flag is 0 1 4 5 Bit 4 Register bank select flag B flag This flag selects a register bank If this flag is 0 register bank 0 is selected if the flag is 1 register bank 1...

Page 24: ...Reserved area Processor interrupt priority level Reserved area Flag register FLG 1 4 10 Bits 12 14 Processor interrupt priority level IPL The processor interrupt priority level IPL consists of three b...

Page 25: ...1 Figure 1 5 1 Configuration of register banks 1 5 Register Bank The R8C Tiny has two register banks each configured with data registers R0 R1 R2 and R3 address registers A0 and A1 and frame base regi...

Page 26: ...ists the content of each register after a reset is cleared Data registers R0 R1 R2 and R3 000016 Address registers A0 and A1 000016 Frame base register FB 000016 Interrupt table register INTB 0000016...

Page 27: ...rd 16 bit integer Signed long word 32 bit integer Unsigned long word 32 bit integer S Sign bit S b31 b0 b31 b0 b15 b0 Figure 1 7 1 Integer data 1 7 Data Types There are four data types integer decimal...

Page 28: ...11 Chapter 1 Overview 1 7 Data Types 1 7 2 Decimal This type of data can be used in DADC DADD DSBB and DSUB Pack format 2 digits Pack format 4 digits Figure 1 7 2 Decimal data b15 b0 b7 b0...

Page 29: ...0 to 15 n 0 to 1 An bit base 8 bit base 16 bit base 8 SB bit base 11 SB bit base 16 SB bit base 8 FB An base 8 An base 16 An Addressing modes Absolute addressing SB based relative addressing FB based...

Page 30: ...7 6 Examples of how to specify bit 2 of address 0000A16 1 Bit specification by bit base Figure 1 7 5 shows the relationship between memory map and bit map Memory bits can be handled as an array of co...

Page 31: ...set to base as the reference 0 and set your desired bit position to bit 3 Address register indirect relative bit specification For address register based indirect addressing use bit 0 of address 00000...

Page 32: ...or word 16 bit data This data type can be used in three types of string instructions character string backward transfer SMOVB instruction character string forward transfer SMOVF instruction and specif...

Page 33: ...8 1 Data Arrangement in Register Figure 1 8 1 shows the relationship between a register s data size and bit numbers b15 b0 b3 b0 b7 b0 MSB LSB b31 b0 Nibble 4 bit data Byte 8 bit data Word 16 bit dat...

Page 34: ...rrangement in memory Does not change 1 8 2 Data Arrangement in Memory Figure 1 8 2 shows data arrangement in memory Figure 1 8 3 shows some examples of operation b7 b0 N DATA N 1 N 2 N 3 b7 b0 N DATA...

Page 35: ...st addressing modes Note however that the immediate data in this op code is a numeric value that can be expressed by 7 to 8 or 8 to 7 varying with instruction Instruction code here is comprised of op...

Page 36: ...table is allocated to addresses 0FFDC16 through 0FFFF16 Figure 1 10 1 shows a fixed vector table The interrupt vector table is comprised of four bytes per table Each vector table must contain the inte...

Page 37: ...ble vector table is comprised of four bytes per table Each vector table must contain the interrupt handler routine s entry address Each vector table has software interrupt numbers 0 to 63 The INT inst...

Page 38: ...Chapter 2 Addressing Modes 2 1 Addressing Modes 2 2 Guide to This Chapter 2 3 General Instruction Addressing 2 4 Special Instruction Addressing 2 5 Bit Instruction Addressing...

Page 39: ...tack pointer relative 2 1 2 Special instruction addressing This addressing accesses an area from address 0000016 through address FFFFF16 and control regis ters The following lists the name of each spe...

Page 40: ...essing mode 3 Explanation Describes the addressing operation and the effective address range 4 Operation diagram Diagrammatically explains the addressing operation 2 1 3 4 2 2 Guide to This Chapter Th...

Page 41: ...6 Absolute abs16 A0 A1 Address register indirect A0 A1 address Memory R0L R1L R0H R1H R0 R1 R2 R3 A0 A1 IMM8 IMM16 IMM20 b7 2 3 General Instruction Addressing Register Memory 2 3 General Instruction A...

Page 42: ...s the value indicated by displacement dsp added including the sign bits constitutes the effective address to be operated on However if the addition resulted in exceeding 0000016 0FFFF16 the bits above...

Page 43: ...d by the content of stack pointer SP plus the value indicated by displacement dsp added including the sign bits constitutes the effective address to be operated on The stack pointer SP here is the one...

Page 44: ...Register Register 2 4 Special Instruction Addressing The value indicated by abs20 constitutes the effective address to be operated on The effective address range is 0000016 to FFFFF16 This addressing...

Page 45: ...g lists the register and instruction combinations that can be used R2R0 R3R1 SHL SHA JMPI and JSRI in structions A1A0 JMPI and JSRI instructions Control register direct INTBL INTBH ISP SP SB FB FLG Th...

Page 46: ...ddress This addressing can be used in JMP instruction If the jump length specifier length is B or W the base address plus the value indicated by displacement dsp added including the sign bits constitu...

Page 47: ...t to be operated on bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 b0 b15 bit R0 Absolute The bit that is as much away from bit 0 at the address indicated by base as the number of bits indicated by b...

Page 48: ...the bits above bit 17 are ignored and the address returns to 0000016 The address range that can be specified by address register A0 A1 is 8 192 bytes from base The bit that is as much away from bit 0...

Page 49: ...tructions The bit that is as much away from bit 0 at the address indicated by frame base register FB plus the value indicated by base added including the sign bit as the number of bits indicated by bi...

Page 50: ...Chapter 3 Functions 3 1 Guide to This Chapter 3 2 Functions...

Page 51: ...ion by showing syntax operation function select able src dest flag changes description examples and related instructions The following shows how to read this chapter by using an actual page as an exam...

Page 52: ...bes the data size in which data is handled The following lists the data sizes that can be speci fied B Byte 8 bits W Word 16 bits L Long word 32 bits Some instructions do not have a size specifier c I...

Page 53: ...e the next page for src dest classified by format 3 2 Functions Chapter 3 Functions Instruction Code Number of Cycles Page 193 Syntax MOV size format src dest Operation dest src Function This instruct...

Page 54: ...side of the slash R1 is the addressing when data is handled in words 16 bits 7 Flag change Indicates a flag change that occurs after the instruction is executed The symbols in the table mean the foll...

Page 55: ...or JSR instruction the assembler chooses the optimum specifier If length is entered its content is given priority The following lists the jump distances that can be specified S 3 bit PC forward relati...

Page 56: ...tion is 128 B or 32768 W otherwise cleared 0 S The flag is set when the operation resulted in MSB 1 otherwise cleared Z The flag is set when the operation resulted in 0 otherwise cleared C The flag is...

Page 57: ...res the result in dest If dest is an A0 or A1 when the size specifier size you selected is B src is zero expanded to perform calculation in 16 bits If src is an A0 or A1 operation is performed on the...

Page 58: ...32768 W or 127 B or 128 B otherwise cleared S The flag is set when the operation resulted in MSB 1 otherwise cleared Z The flag is set when the operation resulted in 0 otherwise cleared C The flag is...

Page 59: ...n adds dest and src together and stores the result in dest If dest is an A0 or A1 when the size specifier size you selected is B src is zero expanded to perform calculation in 16 bits If src is an A0...

Page 60: ...p 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP 2 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 1 If you specify B for the size specifier size...

Page 61: ...1 dsp 8 A0 PC 2 126 label PC 2 129 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 Selectable src dest label This instruction adds dest and src together and stores the result in dest If...

Page 62: ...8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 This...

Page 63: ...16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S format 2 src dest R0L R0H dsp 8 SB dsp 8 FB R0L R0H dsp 8 SB dsp 8 FB abs16 IMM abs...

Page 64: ...ax BAND src Selectable src Flag Change Conditions C The flag is set when the operation resulted in 1 otherwise cleared Description Example BAND flag BAND 4 Ram BAND 16 Ram 16 SB BAND A0 Operation C sr...

Page 65: ...ase 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 C bit base 11 SB 1 1 This dest can only be selected when in S format BCLR Selectable dest Description Example BCLR...

Page 66: ...0 O flag is 0 Bit Move Condition Conditional bit transfer Related Instructions JCnd BMCnd BMCnd Syntax BMCnd dest Operation if true then dest 1 else dest 0 Flag Change Selectable dest dest bit R0 bit...

Page 67: ...n the C flag Selectable src Flag Change Description Example BNAND flag BNAND 4 Ram BNAND 16 Ram 16 SB BNAND A0 Operation ______ C src C src bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 ba...

Page 68: ...he C flag and inverted src together and stores the result in the C flag Selectable src BNOR BNOR Flag Change BNOR flag BNOR 4 Ram BNOR 16 Ram 16 SB BNOR A0 Operation ______ C src C src bit R0 bit R1 b...

Page 69: ...C BTSTS Function dest bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 C bit base 11 SB 1 1 This dest ca...

Page 70: ...d BNTST flag BNTST 4 Ram 8 SB BNTST 16 Ram 16 SB BNTST A0 Related Instructions BCLR BSET BNOT BTST BTSTC BTSTS src bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 base 8 A1 bit base 8 SB bit...

Page 71: ...6 SB BNXOR A0 Operation ______ C src C src bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 C bit base 1...

Page 72: ...A1 base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 C bit base 11 SB Flag Change BOR flag BOR 4 Ram BOR 16 Ram 16 SB BOR A0 Operation C src C U I O B S...

Page 73: ...struction is executed After the interrupt the flags change state as shown on the left Conditions U The flag is cleared I The flag is cleared D The flag is cleared Syntax BRK U I O B S Z D C Instructi...

Page 74: ...g BSET 4 Ram 8 SB BSET 16 Ram 16 SB BSET A0 G S Can be specified dest bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16...

Page 75: ...16 A1 bit base 16 SB bit base 16 C bit base 11 SB 1 1 This src can only be selected when in S format Description Example BTST flag BTST 4 Ram 8 SB BTST 16 Ram 16 SB BTST A0 G S Can be specified Operat...

Page 76: ...e 16 SB bit base 16 C bit base 11 SB BTSTC BTSTC Syntax BTSTC dest Selectable dest BTSTC flag BTSTC 4 Ram BTSTC 16 Ram 16 SB BTSTC A0 Operation Z ________ dest C dest dest 0 Function U I O B S Z D C C...

Page 77: ...16 A1 bit base 16 SB bit base 16 C bit base 11 SB BTSTS BTSTS Function This instruction transfers inverted dest to the Z flag and non inverted dest to the C flag Then it stores 1 in dest Conditions Z...

Page 78: ...e C flag and src together and stores the result in the C flag src bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB b...

Page 79: ...flag bit of the flag register varies depending on the result of subtraction of src from dest If dest is an A0 or A1 when the size specifier size you selected is B src is zero expanded to perform oper...

Page 80: ...A1 A1 1 A0 A1 A0 A0 1 A1 A1 1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1...

Page 81: ...8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0...

Page 82: ...dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 Syntax DADD size src dest U I O B S Z D C Condition...

Page 83: ...0L 1 R0H 1 dsp 8 SB 1 dsp 8 FB 1 abs16 1 A0 2 A1 2 Conditions S The flag is set when the operation resulted in MSB 1 otherwise cleared Z The flag is set when the operation resulted in 0 otherwise clea...

Page 84: ...e you selected is B operation is performed on the 8 low order bits of A0 or A1 If you specify B for the size specifier size the O flag is set when the operation resulted in the quotient exceeding 8 bi...

Page 85: ...selected is B operation is performed on the 8 low order bits of A0 or A1 If you specify B for the size specifier size the O flag is set when the operation resulted in the quotient exceeding 8 bits or...

Page 86: ...remainder has the same sign as the divisor Shown in 1 are the registers that are operated on when you selected B for the size specifier size If src is an A0 or A1 when the size specifier size you sele...

Page 87: ...R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 A0 A0 A1 A1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 1...

Page 88: ...FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I...

Page 89: ...eturn address M Return address H Argument of function SP FB SP After instruction execution Auto variable area Direction in which address increases Number of bytes indicated by src FB L FB H Return add...

Page 90: ...allocates the stack frame and exits from the subroutine Use this instruction in combination with the ENTER instruction The diagrams below show the stack area status before and after the EXITD instruct...

Page 91: ...A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 EXTS B R0L EXTS W R0 B W Operation dest EXT dest U I O B S Z D C Conditions S If...

Page 92: ...tion Example Related Instructions FSET Function dest C D Z S B O I U FCLR Syntax FCLR dest FCLR I FCLR S Operation dest 0 1 The selected flag is cleared to 0 U I O B S Z D C 1 1 1 1 1 1 1 1 This instr...

Page 93: ...le Related Instructions FCLR Function Selectable dest dest C D Z S B O I U Syntax FSET dest Flag Change FSET I FSET S FSET FSET Operation dest 1 U I O B S Z D C 1 1 1 1 1 1 1 1 1 The selected flag is...

Page 94: ...cify B for the size specifier size 2 You can only specify W for the size specifier size dest R0L 1 R0H 1 dsp 8 SB 1 dsp 8 FB 1 abs16 1 A0 2 A1 2 U I O B S Z D C Conditions S The flag is set when the o...

Page 95: ...lags change state as shown on the left U I O B S Z D C Flag Conditions U The flag is cleared if the software interrupt number is 31 or smaller The flag does not change if the software interrupt number...

Page 96: ...saved to the stack area before the INTO instruction is executed After the interrupt the flags change state as shown on the left U I O B S Z D C Conditions U The flag is cleared I The flag is cleared D...

Page 97: ...Jump on Condition Jump on condition Syntax JCnd label Selectable label Description Example JEQ label JNE label Related Instructions BMCnd Function Operation if true then jump label JCnd Flag Change l...

Page 98: ...table label JMP label S B W A Can be specified Operation PC label length label S PC 1 2 label PC 1 9 B PC 1 127 label PC 1 128 W PC 1 32767 label PC 1 32768 A abs20 1 The PC indicates the start addres...

Page 99: ...dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 Flag Change U I O B S Z D C Instruction Code Number of Cycles Page 185 If you selected A for the jump distance specifier length If you selecte...

Page 100: ...is instruction causes control to jump to a subroutine indicated by label Selectable label length label W PC 1 32767 label PC 1 32768 A abs20 W A Can be specified U I O B S Z D C 1 The PC indicates the...

Page 101: ...nce specifier length If you selected A for the jump distance specifier length Function 1 n denotes the number of instruction bytes This instruction causes control to jump to a subroutine at the addres...

Page 102: ...TBL or INTBH make sure that bytes are transferred in succession No interrupt requests are accepted immediately after this instruction LDC R0 SB LDC A0 FB Operation dest src src dest R0L R0 R0H R1 R1L...

Page 103: ...er in abs16 and the start address of table data in abs20 The required register information is specified from table data by the task number and the data in the stack area is transferred to each registe...

Page 104: ...st R0L R0 R0H R1 R1L R2 R1H R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 A0 A0 A1 A1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs...

Page 105: ...LDC STC PUSHC POPC LDINTB LDINTB Syntax LDINTB src Function This instruction transfers src to INTB The LDINTB instruction is a macro instruction consisting of the following LDC IMM INTBH LDC IMM INTB...

Page 106: ...level Syntax LDIPL src Flag Change Description Example LDIPL 2 LDIPL LDIPL Function Selectable src src IMM 1 This instruction transfers src to IPL Operation IPL src U I O B S Z D C 1 The range of valu...

Page 107: ...2 G Q Z S Can be specified B W Operation dest src This instruction transfers src to dest If dest is an A0 or A1 when the size specifier size you selected is B src is zero expanded to transfer data in...

Page 108: ...16 IMM 9 abs16 5 A0 9 A1 9 5 You can only specify B for the size specifier size 6 You cannot choose the same register for src and dest 7 If src is R0L you can only choose A1 for dest as the address re...

Page 109: ...R2 R1H R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 A0 A0 A1 A1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A...

Page 110: ...R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 A0 A0 A1 A1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs1...

Page 111: ...are operated on in 16 bits and the result is stored in 32 bits If you specified R0 R1 or A0 for dest the result is stored in R2R0 R3R1 or A1A0 accordingly MUL B A0 R0L MUL W 3 R0 MUL B R0L R1L MUL W A...

Page 112: ...3 R0 MULU B R0L R1L MULU W A0 Ram U I O B S Z D C This instruction multiplies src and dest together not including the sign bits and stores the result in dest If you selected B for the size specifier s...

Page 113: ...B W Operation dest 0 dest NEG B R0L NEG W A1 U I O B S Z D C Conditions O The flag is set when dest before the operation is 128 B or 32768 W otherwise cleared S The flag is set when the operation resu...

Page 114: ...r 3 Functions No OPeration No operation Flag Change Description Example NOP Function NOP NOP Syntax NOP This instruction adds 1 to PC Operation PC PC 1 U I O B S Z D C Instruction Code Number of Cycle...

Page 115: ...B 1 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 1 dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 Flag Change Description Example G S Can be specified B W NOT B R0L NOT W A1 Conditions S The flag is set when the ope...

Page 116: ...Flag Change OR OR Syntax OR size format src dest Function src dest R0L R0 R0H R1 R1L R2 R1H R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 1 A1 A1 1 A0 A1 A0 A0 1 A1 A1 1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8...

Page 117: ...p 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S format 2 src dest R0L R0H dsp 8 SB dsp 8 FB R0L R0H dsp 8 SB dsp 8 FB abs16 IMM ab...

Page 118: ...1 A1 1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 Description Example Syntax POP size format dest G S Can be specified B W O...

Page 119: ...ble register always be sure to restore INTBH and INTBL in succession No interrupt requests are accepted immediately after this instruction POPC SB Operation dest M SP SP 1 SP 2 U I O B S Z D C 3 3 3 3...

Page 120: ...uction restores the registers selected by dest collectively from the stack area Registers are restored from the stack area in the following order dest 2 R0 R1 R2 R3 A0 A1 SB FB 2 You can choose multip...

Page 121: ...B R0L PUSH W A0 G S Can be specified B W Operation src R0L 1 R0 R0H 1 R1 R1L R2 R1H R3 A0 A0 1 A1 A1 1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1...

Page 122: ...ntax PUSHA src This instruction saves the effective address of src to the stack area PUSHA Ram 8 FB PUSHA Ram 16 SB Operation SP SP 2 M SP EVA src src R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 dsp...

Page 123: ...on This instruction saves the control register indicated by src to the stack area Selectable src src FB SB SP 2 ISP FLG INTBH INTBL Operation SP SP 2 M SP src 1 2 Operation is performed on the stack p...

Page 124: ...n saves the registers selected by src collectively to the stack area The registers are saved to the stack area in the following order src 2 R0 R1 R2 R3 A0 A1 SB FB 2 You can choose multiple src PUSHM...

Page 125: ...ion restores the PC and FLG that were saved when an interrupt request was accepted to return from the interrupt handler routine REIT U I O B S Z D C 1 1 1 1 1 1 1 1 Flag 1 The flags are reset to the p...

Page 126: ...hen the instruction is completed indicates the next address of the last read data If an interrupt request is received during instruction execution the interrupt is acknowledged after a sum of product...

Page 127: ...p 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 ROLC ROLC Flag Change ROLC B R0L ROLC W R0 B W Syntax ROLC size dest Operation This instruction rotates dest one bit to the left including the C flag U I O B S Z...

Page 128: ...6 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 Description Example RORC B R0L RORC W R0 B W Operation This instruction rotates dest one bit to the right including the C flag U I O B S Z...

Page 129: ...t 0 no bits are rotated and no flags are changed If you set a value less than 16 or greater than 16 the result of rotation is indeterminate Operation LSB src 0 src 0 C Function MSB Description Example...

Page 130: ...eturn from subroutine Flag Change Description Example RTS RTS RTS Syntax RTS Operation PCML M SP SP SP 2 PCH M SP SP SP 1 Function Flag Change U I O B S Z D C This instruction causes control to return...

Page 131: ...1 R1L R2 R1H R3 A0 A0 1 A1 A1 1 A0 A1 A0 A0 1 A1 A1 1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB ab...

Page 132: ...ion resulted in 0 the next instruction is executed The op code of this instruction is the same as that of ADJNZ src dest label R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 PC 2 126 label PC 2 129 IMM 1 A0...

Page 133: ...shifted left if negative bits are shifted right If src is an immediate the number of shifts is 8 to 1 and 1 to 8 You cannot set values less than 8 equal to 0 or greater than 8 If src is a register and...

Page 134: ...t of shift is indeterminate Function Description Example SHL B 3 R0L Logically shifted left SHL B 3 R0L Logically shifted right SHL L R1H R2R0 src dest R0L R0 R0H R1 R1L R2 R1H 1 R3 R0L R0 R0H R1 1 R1...

Page 135: ...rder bits of the source address in R1H the 16 low order bits of the source address in A0 the destination address in A1 and the transfer count in R3 The A0 or A1 when the instruction is completed conta...

Page 136: ...der bits of the source address in A0 the destination address in A1 and the transfer count in R3 The A0 or A1 when the instruction is completed contains the next address of the last read data If an int...

Page 137: ...e A0 or A1 when the instruction is completed contains the next address of the last written data If an interrupt request is received during instruction execution the interrupt is acknowledged after one...

Page 138: ...city is 3 bytes If src is not PC the required memory capacity is 2 bytes STC SB R0 STC FB A0 Operation dest src src dest FB SB SP 1 ISP R0L R0 R0H R1 R1L R2 R1H R3 FLG INTBH INTBL A0 A0 A1 A1 A0 A1 ds...

Page 139: ...below Logic 1 indicates a register to be transferred and logic 0 indicates a register that is not transferred Transferred sequentially beginning with FB FB SB A1 A0 R3 R2 R1 R0 MSB LSB abs20 Base addr...

Page 140: ...abs16 dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 Operation dest src B W U I O B S Z D C Conditions S The flag is set whe...

Page 141: ...ple Related Instructions STZ STZX Selectable src dest STNZ STNZ Syntax STNZ src dest This instruction transfers src to dest when the Z flag is 0 STNZ 5 Ram 8 SB src dest IMM8 R0L R0H dsp 8 SB dsp 8 FB...

Page 142: ...ge This instruction transfers src to dest when the Z flag is 1 Description Example Related Instructions STNZ STZX Selectable src dest STZ STZ STZ 5 Ram 8 SB Operation if Z 1 then dest src src dest IMM...

Page 143: ...Flag Change Description Example STZX 1 2 Ram 8 SB Related Instructions STZ STNZ STZX STZX Selectable src dest Operation If Z 1 then dest src1 else dest src2 Function This instruction transfers src1 to...

Page 144: ...16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 Flag Change Description Example SUB B A0 R0L A0 s 8 low order bits and R0L are operated on SUB B...

Page 145: ...p 16 A1 dsp 16 SB abs16 dsp 20 A0 dsp 20 A1 abs20 IMM dsp 20 A0 dsp 20 A1 abs20 SP SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S format 2 src dest R0L R0H dsp 8 SB dsp 8 FB R0L R0H dsp 8 SB dsp 8 FB abs16 IMM ab...

Page 146: ...w order bits of A0 or A1 B W Operation dest src Flag Change Selectable src dest src dest R0L R0 R0H R1 R1L R2 R1H R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 1 A1 A1 1 A0 A1 A0 A0 1 A1 A1 1 A0 A1 dsp 8 A0 ds...

Page 147: ...lags are saved to the stack area before the UND instruction is executed After the interrupt the flag status becomes as shown on the left U I O B S Z D C Conditions U The flag is cleared I The flag is...

Page 148: ...on Example Function WAIT WAIT This instruction halts program execution Program execution is restarted when an interrupt of a higher priority level than IPL is acknowledged or a reset is generated U I...

Page 149: ...placed in src src dest R0L R0 R0H R1 R1L R2 R1H R3 R0L R0 R0H R1 R1L R2 R1H R3 A0 A0 A1 A1 A0 A1 A0 A0 A1 A1 A0 A1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 ds...

Page 150: ...s and R0L are exclusive ORed XOR B R0L A0 R0L is zero expanded and exclusive ORed with A0 XOR B 3 R0L XOR W A0 A1 B W Operation dest dest src Flag Change U I O B S Z D C Conditions S The flag is set w...

Page 151: ...134 Chapter 3 Functions 3 2 Functions Blank for page layout...

Page 152: ...Chapter 4 Instruction Code Number of Cycles 4 1 Guide to This Chapter 4 2 Instruction Code Number of Cycles...

Page 153: ...8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dest 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 DEST dest Rn An dsp 16 SB abs16 dsp 8 An dsp 16 An dsp 8 SB FB An 1 LDI...

Page 154: ...0101 0110 0111 dest code Correspondence Correspondence Correspondence Contents at addresses following start address of instruction 2 See the following figure Content at start address of instruction 0...

Page 155: ...4 5 abs16 dsp 8 An 3 5 dsp 16 An dsp 8 SB FB 3 5 4 5 An 2 5 2 3 2 3 An Rn dest Number of Bytes Number of Cycles ADC dest code dsp8 dsp16 abs16 IMM8 IMM16 size B W SIZE 0 1 dest dsp 8 A0 dsp 8 A1 dsp...

Page 156: ...dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 4 3 4 4 5 4 5 4 6 4 6 4 6 4 4 3 4 3 4 4 5 4 5...

Page 157: ...t Number of Bytes Number of Cycles ADD IMM8 IMM16 size B W SIZE 0 1 dest dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0...

Page 158: ...IMM 8 7 6 5 4 3 2 1 dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1...

Page 159: ...e Number of Cycles ADD Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST dsp 8 SB FB 3 3 2 1 abs16 4 3 dest Number of Bytes Number of Cycles Rn dest code dsp...

Page 160: ...1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An Number of Bytes Number of Cycles dsp 16...

Page 161: ...1 1 0 SIZE 1 1 1 0 1 0 1 1 dsp 8 SB FB 2 3 Rn 1 2 abs16 3 3 Number of Bytes Number of Cycles DEST dest R0L R0H 0 1 src R0L R0H dsp 8 SB dsp 8 FB abs16 Rn dsp 8 SB FB abs16 0 0 0 1 1 0 1 1 src ADD 5 A...

Page 162: ...2 1 IMM IMM4 IMM4 IMM b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 0 1 1 IMM4 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0...

Page 163: ...1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 IMM IMM4...

Page 164: ...1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST Number of Bytes Number of Cycles 5 4 5 4 abs16 dsp 8 An 4 4 dsp 16 An dsp 8 SB F...

Page 165: ...0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles 4 3 4...

Page 166: ...Number of Cycles 4 AND B S src R0L R0H src code dsp8 abs16 dsp 8 SB FB 2 3 Rn 1 2 abs16 3 3 src src SRC R0L R0H dsp 8 SB dsp 8 FB abs16 Rn dsp 8 SB FB abs16 0 0 0 1 1 0 1 1 DEST dest R0L R0H 0 1 AND b...

Page 167: ...1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit An bit base 8 SB FB base 16 An DEST 3 4 bit base 8 SB FB 3 7 3 3 3 3 b...

Page 168: ...151 Chapter 4 Instruction Code Number of Cycles 4 2 Instruction Code Number of Cycles 2 BCLR S bit base 11 SB BCLR dsp8 dest code Number of Bytes Number of Cycles 2 3 b7 b0 0 1 0 0 0 BIT Bytes Cycles...

Page 169: ...1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit An bit base 8 SB FB base 16 An DEST 1 BMCnd dest 0 1 1 1 1 1 1 0 0 0 1 0 DEST...

Page 170: ...0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit An bit base 8 SB...

Page 171: ...bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit An bit base 8 SB FB base 16 An DEST Number of Bytes Number of Cycles dest 3 3 bit base 8 SB FB 3 2 b...

Page 172: ...Rn bit An 2 7 An bit base 16 4 7 4 4 4 4 SRC src base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 src 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0...

Page 173: ...1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit An base 16 An SRC SRC src base 8 A0 base 8 A1...

Page 174: ...e 16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 b...

Page 175: ...t Rn bit An 2 6 An bit base 16 4 6 4 3 4 3 3 6 3 2 SRC src base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 src 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0...

Page 176: ...3 3 bit Rn bit An 2 7 An 4 4 bit base 16 4 4 4 7 DEST dest base 8 A0 base 8 A1 bit base 8 SB bit base 8 FB base 16 A0 base 16 A1 bit base 16 SB bit base 16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0...

Page 177: ...0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit Rn An base 8 An bit base 16 SB bit base 16 bit R0 bit R1 bit R2 bit R3 bit A0 bit A1 A0 A1 bit...

Page 178: ...0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3...

Page 179: ...0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DE...

Page 180: ...e Number of Cycles CMP Number of Bytes Number of Cycles dsp 8 SB FB 3 3 Rn 2 1 abs16 4 3 dest Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST dest code dsp...

Page 181: ...0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16...

Page 182: ...6 DADC 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 0 1 DADC B IMM8 R0L IMM8 Number of Bytes Number of Cycles 3 5 src SRC R0L R0H dsp 8 SB dsp 8 FB abs16 Rn dsp 8 SB FB abs16 0 0 0 1 1 0 1 1 DEST dest R0L R0H 0 1 Nu...

Page 183: ...n Code Number of Cycles DADC 2 DADC W IMM16 R0 Number of Bytes Number of Cycles 4 5 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 3 DADC B R0H R0L Number of Bytes Number of Cycles 2 5 IMM16 DADC 0 1 1 1 1 1 0 1 1 1...

Page 184: ...on Code Number of Cycles DADC 4 DADC W R1 R0 Number of Bytes Number of Cycles 2 5 DADD 1 DADD B IMM8 R0L IMM8 Number of Bytes Number of Cycles 3 5 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 b7 b0 b7 b0 b7 b0 b7...

Page 185: ...n Code Number of Cycles DADD 2 DADD W IMM16 R0 IMM16 Number of Bytes Number of Cycles 4 5 DADD 3 DADD B R0H R0L Number of Bytes Number of Cycles 2 5 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 b7 b0 b7 b0 0 1 1 1...

Page 186: ...tes Number of Cycles 2 5 DEC 1 DEC B dest dest code dsp8 abs16 Number of Bytes Number of Cycles dsp 8 SB FB 2 3 Rn 1 1 abs16 3 3 dest Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp...

Page 187: ...umber of Bytes Number of Cycles DEST dest A0 A1 0 1 b7 b0 1 1 1 1 DEST 0 1 0 b7 b0 b7 b0 0 1 1 1 1 1 0 SIZE 1 1 1 0 0 0 0 1 IMM8 IMM16 Bytes Cycles Bytes Cycles 1 If the size specifier size is W the n...

Page 188: ...24 4 24 abs16 dsp 8 An 3 24 dsp 16 An dsp 8 SB FB 3 24 4 24 An 2 24 2 22 2 22 An Rn src DIVU 1 DIVU size IMM IMM8 IMM16 size B W SIZE 0 1 3 18 Number of Bytes Number of Cycles b7 b0 b7 b0 0 1 1 1 0 1...

Page 189: ...es Number of Cycles dsp 16 SB 4 20 4 20 abs16 dsp 8 An 3 20 dsp 16 An dsp 8 SB FB 3 20 4 20 An 2 20 2 18 An Rn src DIVX 1 DIVX size IMM IMM8 IMM16 size B W SIZE 0 1 3 22 b7 b0 b7 b0 b7 b0 b7 b0 0 1 1...

Page 190: ...6 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An SRC SRC size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB abs16 dsp 8 An 3 24 dsp 16 An dsp 8 SB FB 3 24 4 24 An 2 24 2 22 2 22 An Rn s...

Page 191: ...n Code Number of Cycles DSBB 2 DSBB W IMM16 R0 IMM16 Number of Bytes Number of Cycles 4 4 DSBB 3 DSBB B R0H R0L Number of Bytes Number of Cycles 2 4 b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 b7 b0 b...

Page 192: ...on Code Number of Cycles DSBB 4 DSBB W R1 R0 Number of Bytes Number of Cycles 2 4 DSUB Number of Bytes Number of Cycles 3 4 1 DSUB B IMM8 R0L IMM8 b7 b0 b7 b0 b7 b0 b7 b0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0...

Page 193: ...n Code Number of Cycles DSUB 2 DSUB W IMM16 R0 IMM16 Number of Bytes Number of Cycles 4 4 DSUB 3 DSUB B R0H R0L Number of Bytes Number of Cycles 2 4 b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 b7 b0 b...

Page 194: ...tion Code Number of Cycles DSUB 4 DSUB W R1 R0 Number of Bytes Number of Cycles 2 4 1 ENTER IMM8 Number of Bytes Number of Cycles 3 4 IMM8 ENTER b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 b7 b0 b7 b0...

Page 195: ...4 5 Rn An dsp 8 An 3 5 dest DEST dest dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 DEST dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1...

Page 196: ...2 EXTS W R0 Number of Bytes Number of Cycles 2 3 Number of Bytes Number of Cycles 2 2 FCLR 1 FCLR dest DEST C D Z S B O I U 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 b7 b0 b7 b0 0 1 1 1 1 1 0 0...

Page 197: ...est dest code dsp8 abs16 dest DEST C D Z S B O I U 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST Number o...

Page 198: ...s 4 2 Instruction Code Number of Cycles INC 2 INC W dest INT 1 INT IMM 11 Number of Bytes Number of Cycles 2 19 DEST dest A0 A1 0 1 1 0 1 1 DEST 0 1 0 b7 b0 1 1 Number of Bytes Number of Cycles b7 b0...

Page 199: ...1 0 0 1 1 GEU C GTU EQ Z N Cnd CND 1 0 0 1 0 1 1 1 0 1 1 1 LTU NC LEU NE NZ PZ Number of Bytes Number of Cycles 2 2 b7 b0 1 1 1 1 0 1 1 0 b7 b0 dsp8 address indicated by label start address of instru...

Page 200: ...of Bytes Number of Cycles Cnd CND 1 0 0 0 1 0 0 1 1 0 1 0 LE O GE CND 1 1 0 0 1 1 0 1 1 1 1 0 b7 b0 b7 b0 dsp8 address indicated by label start address of instruction 2 0 1 1 1 1 1 0 1 1 1 0 0 CND GT...

Page 201: ...e Number of Bytes Number of Cycles 2 4 JMP 3 JMP W label label code Number of Bytes Number of Cycles 3 4 b7 b0 dsp8 address indicated by label start address of instruction 1 dsp8 1 1 1 1 1 1 1 0 b7 b0...

Page 202: ...1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 20 An dsp 16 SB abs16 R0 R1 R2 R3 A0 A1 A0 A1 An SRC Number of Bytes Number of Cyc...

Page 203: ...1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 20 An dsp 16 SB abs16 An Number of Bytes Number of Cycles dsp 16 SB 4 10 4...

Page 204: ...les JSR 1 JSR W label dsp16 address indicated by label start address of instruction 1 label code 3 8 2 JSR A label Number of Bytes Number of Cycles 4 9 dsp16 b7 b0 1 1 1 1 0 1 0 1 Number of Bytes Numb...

Page 205: ...n dsp 8 SB FB 3 15 5 15 An 2 15 2 11 2 11 An Rn src src dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 20 A0 dsp 20 A1 dsp 16 SB abs16 SRC src 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1...

Page 206: ...ytes Number of Cycles dsp 16 SB 4 3 4 3 abs16 dsp 8 An 3 3 dsp 16 An dsp 8 SB FB 3 3 4 3 An 2 3 2 1 2 1 An Rn src Rn An An 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 R0 R1 R2 R3 A...

Page 207: ...ber of Cycles 4 2 Instruction Code Number of Cycles LDCTX 1 LDCTX abs16 abs20 abs16 7 11 2 m b7 b0 b7 b0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 Number of Bytes Number of Cycles abs20 Bytes Cycles 2 m denotes...

Page 208: ...8 SB FB 6 5 7 5 An 5 5 5 4 5 4 An Rn dest LDE dest dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0...

Page 209: ...dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 5 4 5 abs16 dsp 8 An 3 5 dsp 16 An dsp 8 SB F...

Page 210: ...0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST Number of Bytes Number of Cycles dsp...

Page 211: ...1 2 3 4 5 6 7 IMM IMM4 IMM4 IMM 8 7 6 5 4 3 2 1 dest dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0...

Page 212: ...e Number of Cycles MOV dsp 8 SB FB 3 2 Rn 2 1 abs16 4 2 dest Number of Bytes Number of Cycles Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST IMM8 3 MOV B...

Page 213: ...Z 0 dest dsp 8 SB FB 2 2 Rn 1 1 abs16 3 2 dest Number of Bytes Number of Cycles Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST MOV b7 b0 1 SIZE 1 0 DEST 0...

Page 214: ...1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 2 4 2 4 3 5 3 5 3 6 3...

Page 215: ...e dsp8 abs16 src SRC R0L R0H dsp 8 SB dsp 8 FB abs16 Rn dsp 8 SB FB abs16 0 0 0 1 1 0 1 1 R0L R0H 0 1 SRC src dest DEST dsp 8 SB dsp 8 FB abs16 0 1 1 0 1 1 dsp 8 SB FB 2 3 Rn 1 2 abs16 3 3 src Number...

Page 216: ...0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 5 3 5 3 abs16 dsp 8 An...

Page 217: ...A1 An SRC SRC size B W SIZE 0 1 dsp 16 SB 5 4 5 4 abs16 dsp 8 An 4 4 dsp 16 An dsp 8 SB FB 4 4 5 4 An 3 4 3 3 3 3 An Rn dest 1 MOVA src dest dsp8 src code dsp16 3 2 dsp 16 SB 4 2 dsp 16 An dsp 8 SB FB...

Page 218: ...abs16 DEST dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0H...

Page 219: ...16 SRC src 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0H...

Page 220: ...n An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R1 R1L A0 A0 A1 An size B W SIZE 0 1 dsp 16 SB 5 5 5 5 abs16 dsp 8 An 4 5 dsp 16 An dsp 8 SB FB 4 5 5 5 An 3 5 3 4 3 4 An Rn dest Number of B...

Page 221: ...1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R1 R1L A0 A0 A1 An Number of Bytes Number of Cycles dsp 16 SB 4 5 4 5 4 6 5 6 5 6 6 6 6 6 6 6 abs16 dsp 8 An 3 5 3 5 3 6 4 6 4 6 5 6 5...

Page 222: ...SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R1 R1L A0 A0 A1 An dest code dsp8 dsp16 abs16 IMM8 IMM16 dsp 16 SB 5 5 5 5 abs16 dsp 8 An 4 5 dsp 16 An 4 5 5 5 An 3 5 3 4 3 4 An Rn dest b7 b0 b7 b0 0 1 1 1 1...

Page 223: ...1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R1 R1L A0 A0 A1 An dsp 16 SB 4 5 4 5 4 6 5 6 5 6 6 6 6 6 6 6 4 5 4 5 4 6 5 6 5 6 6 6 6 6 6 6 abs16 dsp 8 An 3 5 3 5 3 6 4 6 4 6 5 6 5...

Page 224: ...1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1...

Page 225: ...1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number of Cycles dsp...

Page 226: ...dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 5 4 5 4 abs16 dsp 8 An 4 4 dsp 16 An dsp 8 SB FB 4 4 5 4 An 3 4 3 2 3...

Page 227: ...1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 4 3 4 4 5 4 5 4 6 4 6...

Page 228: ...0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 1...

Page 229: ...ction Code Number of Cycles 2 POP B S dest 1 3 POP 3 POP W S dest 1 3 Number of Bytes Number of Cycles DEST dest R0L R0H 0 1 DEST dest A0 A1 0 1 POP b7 b0 1 0 0 1 DEST 0 1 0 b7 b0 1 1 0 1 DEST 0 1 0 N...

Page 230: ...B SB R3 R2 R1 R0 A1 A0 DEST 2 Number of Bytes Number of Cycles 2 3 Number of Bytes Number of Cycles 2 The bit for a selected register is 1 The bit for a non selected register is 0 b7 b0 b7 b0 1 1 1 0...

Page 231: ...1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An SRC SRC Number of Bytes Number of Cycles dsp 16 SB 4 4...

Page 232: ...ruction Code Number of Cycles PUSH 3 PUSH B S src 1 2 Number of Bytes Number of Cycles PUSH 4 PUSH W S src 1 2 SRC src R0L R0H 0 1 SRC src A0 A1 0 1 b7 b0 1 0 0 0 SRC 0 1 0 b7 b0 1 1 0 0 SRC 0 1 0 Num...

Page 233: ...of Cycles SRC src dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs1...

Page 234: ...of Cycles 1 PUSHM src SRC 2 2 m REIT 1 REIT 1 6 Number of Bytes Number of Cycles src R0 R1 A0 A1 SB FB R2 R3 SRC 1 b7 b0 1 1 1 0 1 1 0 0 b7 b0 1 1 1 1 1 0 1 1 2 m denotes the number of registers to b...

Page 235: ...B abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0...

Page 236: ...0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3...

Page 237: ...st 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1...

Page 238: ...0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1L R2 R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3...

Page 239: ...1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B...

Page 240: ...1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 4 3 4 4 5 4 5 4 6 4 6...

Page 241: ...0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DE...

Page 242: ...6 A0 dsp 16 A1 dsp 16 SB abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An...

Page 243: ...R0H R1L R2 R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 m 4 3 m abs16 dsp 8 An 3 3 m dsp 16 An dsp 8 SB FB 3 3 m 4 3 m An 2 3 m 2 2 m 2 2 m An Rn dest SHA 3 SHA L...

Page 244: ...r of Cycles 4 2 Instruction Code Number of Cycles SHA 4 SHA L R1H dest 2 4 m Number of Bytes Number of Cycles DEST dest 0 1 b7 b0 b7 b0 1 1 1 0 1 0 1 1 0 0 1 DEST 0 0 0 1 R2R0 R3R1 1 m denotes the num...

Page 245: ...6 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R...

Page 246: ...e B W SIZE 0 1 dsp 16 SB 4 3 m abs16 dsp 8 An 3 3 m dsp 16 An dsp 8 SB FB 3 3 m 4 3 m An 2 3 m 2 2 m 2 2 m An Rn dest Number of Bytes Number of Cycles SHL 3 SHL L IMM dest Number of Bytes Number of Cy...

Page 247: ...Number of Cycles SMOVB 1 SMOVB size size B W SIZE 0 1 2 5 5 m Number of Bytes Number of Cycles DEST dest R2R0 R3R1 0 1 1 m denotes the number of shifts performed b7 b0 b7 b0 1 1 1 0 1 0 1 1 0 0 0 DES...

Page 248: ...size B W SIZE 0 1 2 5 5 m Number of Bytes Number of Cycles 1 SMOVF size SSTR 0 1 1 1 1 1 0 SIZE 1 1 1 0 1 0 1 0 1 SSTR size size B W SIZE 0 1 2 3 2 m Number of Bytes Number of Cycles 1 m denotes the...

Page 249: ...DEST Number of Bytes Number of Cycles dsp 16 SB 4 2 4 2 abs16 dsp 8 An 3 2 dsp 16 An dsp 8 SB FB 3 2 4 2 An 2 2 2 1 2 1 An Rn dest Bytes Cycles STC 2 STC PC dest dest Code dsp8 dsp16 abs16 DEST dest d...

Page 250: ...1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An SRC SRC size B W SIZE 0 1 Number of Bytes Number of Cy...

Page 251: ...7 4 7 4 abs16 dsp 8 An 6 4 dsp 16 An dsp 8 SB FB 6 4 7 4 An 5 4 5 3 5 3 An Rn src dsp8 src code dsp16 abs16 src dsp 8 A0 dsp 8 A1 dsp 8 SB dsp 8 FB dsp 16 A0 dsp 16 A1 dsp 16 SB abs16 src 0 0 0 0 0 0...

Page 252: ...DEST dsp 8 SB FB 3 2 Rn 2 1 abs16 4 2 dest Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST Number of Bytes Number of Cycles Number of Bytes Number of Cycle...

Page 253: ...1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W...

Page 254: ...e Number of Cycles SUB 2 SUB B S IMM8 dest dsp 8 SB FB 3 3 Rn 2 1 abs16 4 3 dest Rn dsp 8 SB FB 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R0H R0L dsp 8 SB dsp 8 FB abs16 abs16 dest DEST b7 b0 1 0 0 0 1 DEST IMM8...

Page 255: ...1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 4 3 4 4 5 4 5 4 6 4...

Page 256: ...0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B W SIZE 0 1 Number of Bytes Number...

Page 257: ...1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16 SB 4 3 4 3 4 4 5 4 5 4 6 4 6...

Page 258: ...of Cycles 4 2 Instruction Code Number of Cycles 1 UND UND Number of Bytes Number of Cycles 1 20 Bytes Cycles 1 WAIT Number of Bytes Number of Cycles 2 3 Bytes Cycles WAIT b7 b0 1 1 1 1 1 1 1 1 b7 b0...

Page 259: ...16 A0 dsp 16 A1 dsp 16 SB abs16 dest 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 A...

Page 260: ...1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An DEST DEST size B...

Page 261: ...0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rn An dsp 8 An dsp 8 SB FB dsp 16 An dsp 16 SB abs16 R0L R0 R0H R1 R1L R2 R1H R3 A0 A1 A0 A1 An size B W SIZE 0 1 Number of Bytes Number of Cycles dsp 16...

Page 262: ...hapter 5 Interrupt 5 1 Outline of Interrupt 5 2 Interrupt Control 5 3 Interrupt Sequence 5 4 Return from Interrupt Routine 5 5 Interrupt Priority 5 6 Multiple Interrupts 5 7 Precautions for Interrupts...

Page 263: ...branches to the interrupt routine that is set to an inter rupt vector table Each interrupt vector table must have had the start address of its corresponding interrupt routine set For details about the...

Page 264: ...1 the U flag is saved when the INT instruction is executed and the U flag is cleared to 0 to choose the interrupt stack pointer ISP before executing the interrupt sequence The previous U flag before t...

Page 265: ...t refer to the R8C s Hardware Manual 3 Single step interrupt This interrupt is used exclusively for development support tools Do not use this interrupt 4 Address match interrupt When any one of AIER0...

Page 266: ...he flag is changed by an REIT instruction the changed status takes effect beginning with that REIT instruction If the flag is changed by an FCLR FSET POPC or LDC instruction the changed status takes e...

Page 267: ...et by the ILVL2 to ILVL0 bits Table 5 2 1 shows how interrupt priority levels are set Table 5 2 2 shows interrupt enable levels in relation to IPL The following lists the conditions under which an int...

Page 268: ...pt not requested it may not actually be cleared to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 3 When disabling interrupts using the I flag set the I f...

Page 269: ...e I flag the D flag and the U flag of the FLG register are as follows The I flag is set to 0 interrupt disabled The D flag is set to 0 single step interrupt is disabled The U flag is set to 0 ISP is s...

Page 270: ...d Time a varies with each instruction being executed The DIVX instruction requires a maximum time that consists of 30 cycles without wait state cycle number in case the divisor is register b The addre...

Page 271: ...be saved save them in program at the beginning of the interrupt routine The PUSHM instruction allows you to save all registers except the SP by a single instruction 5 3 Interrupt Sequence Figure 5 3...

Page 272: ...stack area immediately preceding the interrupt sequence are automati cally restored Then control returns to the routine that was under execution before the interrupt request was acknowledged If there...

Page 273: ...between these interrupts is resolved by the priority that is set in hardware Special interrupts such as the watchdog timer interrupt have their priority levels set in hardware Figure 5 5 1 lists the i...

Page 274: ...n the interrupt routine you can reenable interrupts so that an interrupt request can be acknowledged that has higher priority than the processor interrupt priority level IPL Figure 5 6 1 shows how mul...

Page 275: ...ledged because of low interrupt priority Main routine instructions are not executed Interrupt request generated Nesting Main routine Reset Time Interrupt 1 Interrupt 1 Interrupt 2 Figure 5 6 1 Multipl...

Page 276: ...r are generated If interrupt requests managed by any interrupt control register are likely to occur disable the interrupts before changing the interrupt control register 2 To modify any interrupt cont...

Page 277: ...egister to 0016 NOP NOP FSET I Enable interrupts Example 2 Use dummy read to have FSET instruction wait INT_SWITCH2 FCLR I Disable interrupts AND B 00H 0056H Set TXIC register to 0016 MOV W MEM R0 Dum...

Page 278: ...Chapter 6 Calculation Number of Cycles 6 1 Instruction queue buffer...

Page 279: ...ntil all of the instruction codes required for program execution are avail able Furthermore the number of read cycles increases in the following cases 1 The number of read cycles increases as many as...

Page 280: ...P 40 04 00 40 64 64 04 DR 0C06C 64 73 F1 00 40 64 00 40 04 73 FF 00 0C06D 04001 04000 0C06F 0C06E 0C073 0C072 0C074 AA AA 04 P P P P P P 04 73 FF 00 Content at jump address is prefetched at the same t...

Page 281: ...nd the answer to it are given on one page the upper section is for the question and the lower section is for the answer if a pair of question and answer extends over two or more pages a page number is...

Page 282: ...same manner so you can use them as intended in programming in the assembly language If you write a program in C use FB as a stack frame base register How do I distinguish between the static base regi...

Page 283: ...y out of control if an interrupt request occurs in changing the value of INTB So it is not recommended to frequently change the value of INTB while a program is being executed Is it possible to change...

Page 284: ...When several tasks run the OS secures stack areas to save registers of individual tasks Also stack areas have to be secured task by task to be used for handling interrupts that occur while tasks are...

Page 285: ...e 16 The relation between the 2 lower order bytes and bit base 16 is as follows 2 lower order bytes base 16 8 bit For example in the case of BSET 2 0AH setting bit 2 of address 000A16 to 1 the 2 lower...

Page 286: ...uotient divisor dividend and remainder holds dividend divisor quotient remainder Since the sign of the remainder is different between these instructions the quotient obtained either by dividing a posi...

Page 287: ...Glossary 1 Glossary Technical terms used in this software manual are explained below They are good in this manual only...

Page 288: ...ion in terms of decimal system displacement The difference between the initial position and later position effective address An after modification address to be actually used extention area For the R8...

Page 289: ...h an operation is performed A generic term for move comparison bit processing shift rotation arithmetic logic and branch A part of instruction code that indicates what sort of operation the instructio...

Page 290: ...For example sign extending FF16 results in FFFF16 and sign extending 0F16 results in 000F16 An area for automatic variables the functions of the C language use A sequence of characters To restore comb...

Page 291: ...Symbol 1 Table of symbols Symbols used in this software manual are explained below They are good in this manual only...

Page 292: ...xtension H Higher order byte of a register or memory H4 Four higher order bits of an 8 bit register or 8 bit memory Absolute value L Lower order byte of a register or memory L4 Four lower order bits o...

Page 293: ...e 37 dest 18 F FB 5 Fixed vector table 19 Flag change 37 Flag register 5 FLG 5 Frame base register 5 Function 37 I Interrupt table register 5 I flag 6 Instruction code 138 Instruction Format 18 Instru...

Page 294: ...bank select flag 6 Register bit 12 Related instruction 37 Reset 9 S S flag 6 SB 5 Selectable src dest label 37 Sign flag 6 Size specifier 35 Software interrupt number 20 src 18 Stack pointer 5 Stack...

Page 295: ...REVISION HISTORY R8C Tiny Series SOFTWARE MANUAL Rev Date Description Page Summary B 1 1 00 Jun 19 03 First Edition...

Page 296: ...ONDUCTORS SOFTWARE MANUAL R8C Tiny Series Rev 1 00 Editioned by Committee of editing of RENESAS Semiconductor Software Manual This book or parts thereof may not be reproduced in any form without permi...

Page 297: ...R8C Tiny Series Software Manual 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan...

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