R8C/18 Group, R8C/19 Group
Rev.1.30
Apr 14, 2006
Page 142 of 233
REJ09B0222-0130
Figure 14.30
Operating Example in Input Capture Mode
FFFFh
0000h
C
ount
e
r c
o
n
ten
ts
(h
e
x
)
Count starts
Overflow
Period
TCC00 bit in
TCC0 register
1
0
Measured pulse
(TCIN pin input)
Transmit timing from
timer C counter to
TM0 register
IR bit in
INT3IC register
The above applies under the following conditions.
TCC0 register TCC04 to TCC03 bits = 01b (capture input polarity is set for falling edge).
TCC07 = 0 (INT3/TCIN input as capture input trigger)
←
Measurement value1
←
Measurement value 2
←
Set to 1 by program
Transmit
(measured
value 1)
The delay caused by digital filter and
one count source cycle delay (max.)
Measured
value 1
TM0 register
Measured value 2
Measured
value 3
Indeterminate
Set to 0 when interrupt request
is acknowledged, or set by
program
IR bit in
TCIC register
Set to 0 by
program
Set to 0 when interrupt request is acknowledged, or set by program
Transmit
(measured value 2)
Transmit
(measured value 3)
Indeterminate
1
0
1
0
1
0
Measurement
value 3
1
0
