R8C/18 Group, R8C/19 Group
12. Interrupts
Rev.1.30
Apr 14, 2006
Page 85 of 233
REJ09B0222-0130
12.2
INT Interrupt
12.2.1
INT0 Interrupt
The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in
the INTEN register is set to 1 (enable). The edge polarity is selected using the INT0PL bit in the
INTEN register and the POL bit in the INT0IC register.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the external trigger input pin of timer Z.
Figure 12.11 shows Registers INTEN and INT0F.
Figure 12.11
Registers INTEN and INT0F
INT0
______
Input Filter Select Register
Symbol
Address
After Reset
INT0F
001Eh
00h
Bit Symbol
Bit Name
Function
RW
INT0
_____
input filter select bits
—
(b7-b3)
—
(b2)
Set to 0.
0
RW
Reserved bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
—
b3 b2 b1 b0
b7 b6 b5 b4
INT0F0
RW
INT0F1
RW
External Input Enable Register
Symbol
Address
After Reset
INTEN
0096h
00h
Bit Symbol
Bit Name
Function
RW
INT0
_____
input enable bit
(1)
INT0
_____
input polarity select bit
(2, 3)
NOTES:
1.
2.
3.
0
—
(b7-b2)
Set the INT0EN bit w hile the INOSTG bit in the PUM register is set to 0 (one-shot trigger disabled).
b3 b2 b1 b0
b7 b6 b5 b4
0 0 0
RW
0 0
RW
INT0EN
When setting the INT0PL bit to 1 (both edges), set the POL bit in the INT0IC register to 0 (selects falling edge).
The IR bit in the INT0IC register may be set to 1 (requests interrupt) w hen the INT0PL bit is rew ritten. Refer to
12.5.5
Changing Interrupt Sources
.
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
Set to 0.
Reserved bits
RW
INT0PL
