R8C/18 Group, R8C/19 Group
17. Flash Memory Version
Rev.1.30
Apr 14, 2006
Page 193 of 233
REJ09B0222-0130
17.4.5
Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the
occurrence of an error. Therefore, checking these status bits (full status check) can be used to
determine the execution result.
Table 17.6 lists the Errors and FMR0 Register Status. Figure 17.15 shows the Full Status Check and
Handling Procedure for Individual Errors.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
Table 17.6
Errors and FMR0 Register Status
FRM00 Register (Status
Register) Status
Error
Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1
1
Command
sequence error
• When a command is not written correctly.
• When invalid data other than that which can be written
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)
• When the program command or block erase command
is executed while rewriting is disabled using the FMR02
bit in the FMR0 register, or the FMR15 or FMR16 bit in
the FMR1 register.
• When an address not allocated in flash memory is input
during erase command input.
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write the block for which rewriting
is disabled during write command input.
1
0
Erase error
• When the block erase command is executed but
auto-erasure does not complete correctly.
0
1
Program error
• When the program command is executed but
auto-programming does not complete correctly.
