Raisecom Technology Co., Ltd
16
Clock
1
st
Clock
2
nd
Timeslot
Follow
Error
Code
Test
Phase 1
st
Tributary
Bidirectional
loopback
2
nd
Tributary
Bidirectional
loopback
Loop back
position
ON *
*
√
√
Reverse
√
√
Local
OFF *
*
×
×
Positive
×
×
Remote
1. The 1
st
and 2
nd
bit: Clock mode choosing dip-switch Timing1, Timing2 (default is
ON)
The Clock mode is defined by the 1
st
bit and 2
nd
bit of SW5, detail is shown in below table:
SW5-1
SW5-2
Clock Mode
OFF
OFF
Master Clock (Internal clock)
OFF ON
ON OFF
V.35 terminal Clock ( Follow V.35 interface
clock)
ON
ON
Slave Clock ( Follow fiber line clock)
2. The 3
rd
bit: Timeslot auto follow function TS_FLOW (default OFF)
SW5-3
Timeslot auto follow function
ON Enable
OFF Disable
To make local timeslot follow remote timeslot, below three conditions should be ensured:
(1) This series device is used point to point in pair.
(2) There is no PCM device which occupy the Sa bit linked in E1 line.
(3) Local device works on slave clock mode.
When all of above condition is satisfied, setting the SW5-3 of local device as ON to open
timeslot auto-follow function, the timeslot and frame mode (PCM30/PCM31) of local
device will follow the configurations of remote device automatically.
3. The 4
th
bit: Error code test function choosing dip-switch BET (default OFF)
SW5-4
Internal Error Code Test Function
ON Enable
OFF Disable
There is an error code test unit inside this series device, and the main purpose of this unit
is producing pseudo random sequence (2E15-1 STD) and sending them to optical line.
This sequence can be uploaded to proper data channel by configuration, and then via
many loopback modes the returned sequence is sent to device for testing. The testing
result will be displayed by the PWR/PAT indicator on front panel. When error code is
captured the PWR/PAT indicator will turn to green and keep for at least one second. If
there is no new error code occurs the PWR/PAT indicator will come back to steady yellow
status.
