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The next table shows {ProductNameShort} interrupt assignments. This routing is
implemented by the RadiSys 82600 embedded chipset.
1
You cannot move these items.
2
You can include these items in the PCI interrupt pool.
For detailed information, see
Chapter 4, BIOS Configuration
.
B
Interrupts
Table B-1. Interrupts
Interrupt
Description
IRQ0
1
System timer (internal connection)
IRQ1
1
Keyboard controller (internal connection)
IRQ2
Cascade interrupt input (internal connection)
IRQ3
2
IRQ4
1, 2
COM1 (internal connection)
IRQ5
2
IRQ6
IRQ7
IRQ8
1
Real-time clock (internal connection)
IRQ9
1, 2
SMBus, reset switches, power management, DMA, BIST (via Serial IRQ)
IRQ10
2
Soft reset is imminent via serial IRQ from Watchdog
IRQ11
2
IRQ12
1, 2
PS/2 (internal connection)
IRQ13
Numeric coprocessor ~FERR (internal connection)
IRQ14
1
Primary IDE channel
IRQ15
2
NMI
1
When ~SERR or ~IOCHK is asserted (software controlled)
SMI
Power management or ECC error
PIRQA
Intel 82546 Ethernet controller, channel 1
PIRQB
Intel 82546 Ethernet controller, channel 2
PIRQC
PIRQD
1
Note
Note that PIRQ[A–D] correspond directly to the PCI interrupts INT[A–D]. The software may steer these
interrupts to any of the 11 interrupts (IRQ[15, 14, 12–9, 7–3]) using the Interrupt Route Control register.
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