RadiSys EPC-3307 Hardware Reference Manual Download | Manualshive

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Chapter 4: Theory of operation

61

COM ports

The Super I/O includes two RS-232 compatible serial ports. The Super I/O chip
includes 16C550 compatible UARTs with separate send and receive 16-byte FIFOs.

•

COM 1

: Configured at I/O addresses 3F8–3FFh and uses IRQ4, COM 1 signals

pass through an RS232 transceiver IC and out the front panel via an RJ45
connector, as well as a 10-pin header on the RTM.

•

COM 2

: Configured at I/O addresses 2F8–2FFh and uses IRQ3, COM 2 signals

are available via a standard DB9 connection. The COM 2 connector can only be
accessed by the use of an RTM.

This transceiver’s I/O pins meet the electrical portion of the EIA/TIA-232-E
specification as well as EIA/TIA-232-E. COM 1 signals also go out CompactPCI

J3

connector.

The Super I/O chip allows relocation of these ports to the COM 3 and/or COM 4
standard I/O addresses, respectively. If so configured, COM 3 and COM 4 use I/O
addresses 3E8–3EFh and 2E8–2EFh respectively. If not needed, you can disable these
serial ports in the BIOS setup program’s

I/O Device Configuration sub-menu

to free

the I/O address and interrupt for usage by other expansion products.

Keyboard and mouse controller

The Super I/O provides an integrated keyboard and mouse controller. The Super I/O
keyboard controller, located at I/O locations 60–64h, is functionally equivalent to
the industry standard 8042A controller.

The keyboard interrupt connects to IRQ1. If enabled, the mouse interrupt utilizes
IRQ12. The keyboard and mouse connectors are located on the RTM. For more
information about the RTM, see

Appendix E, Rear Transition module (RTM)

.

IPMI baseboard management controller (BMC)

The EPC-3307 implements an IPMI Baseboard Management Controller (BMC) in
compliance with the PICMG 2.9 R1.0 CompactPCI System Management
Specification. This IPMI BMC provides the ability to monitor, query, and log
system management events on the EPC-3307 and in the CompactPCI system. This
capability provides the ability to detect failing hardware, log the sequence of events
leading to a failure and remotely manage and reset the system.

The EPC-3307 BMC is implemented using the KBC interface mechanism at I/O
locations 0xCA2/3. In order to support legacy RadiSys utilities, I/O locations
0xCA0/1 are also directed to the BMC.

Do not use both the front and rear connections to COM 1 at the same time.
Only one connection to COM 1 may be used at a time.

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Summary of Contents for EPC-3307

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...03 615 1121 Toll Free 800 950 0044 International Headquarters Gebouw Flevopoort Televisieweg 1A NL 1322 AC Almere The Netherlands Phone 31 36 5365595 Fax 31 36 5365620 007 01243 0003 Myy 2002 EPC 3307 Hardware Reference Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...tion DAVID MAUI OS 9 SoftStax and OS 9000 are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak Hawk and UpLink are trademarks of RadiSys Microware Communications Software Division Inc All other trademarks registered trademarks service marks and trade names are the property of their respective owners Artisan Technology Group Quality Instrumentation Guaranteed ...

Page 4: ...ave sub menus 16 Keyboard Features sub menu 21 UBE Shadow Control sub menu 23 About shadow memory regions 23 Advanced menu 25 Console Redirection sub menu 29 I O Device Configuration sub menu 31 PCI Configuration sub menu 33 Cache Memory sub menu 34 Advanced Chipset Control sub menu 39 Boot menu 40 Exit menu 41 CMOS Save and Restore sub menu 43 Chapter 4 Theory of operation Organization 46 Block d...

Page 5: ...ttery 60 Super I O 60 Floppy disk 60 COM ports 61 Keyboard and mouse controller 61 IPMI baseboard management controller BMC 61 HDD Option 62 Special features 62 CPLD ISA interface 62 Watchdog timer 63 Front panel red green LED 64 Last Reset Source 65 Local interrupt control register 65 Reset controller 66 Hot Swap signals 67 CompactPCI features register 67 IPMI special utility 68 BIOS bank switchi...

Page 6: ...odule RTM Features 109 Block diagram 110 CPU board I O 110 Installing and configuring the RTM 111 Inserting the RTM 111 Removing the RTM 112 Connectors 113 Connector locations 113 Backplane J3 114 Backplane J5 115 Ethernet 115 COM 1 header 116 COM 2 116 IDE secondary 117 Keyboard mouse 117 PIM PMC I O module 118 USB 120 Appendix F PMC modules Installing a PMC module on the main board 121 Disconnec...

Page 7: ... phlash exe to re program the flash chip 129 Using BIOS configuration options to re program the flash chip 130 Using jumpers to re program the flash chip 131 Glossary 133 Index 141 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 8: ...0 Advanced Chipset Control sub menu 39 Figure 3 11 Boot menu 40 Figure 3 12 Exit menu 41 Figure 3 13 CMOS Save and Restore sub menu 43 Figure 4 1 EPC 3307 block diagram 46 Figure 4 2 Flash boot device memory 49 Figure 4 2 EPC 3307 CT architecture 55 Figure 4 3 BIOS paging 69 Figure C 1 EPC 3307 Main board connectors 86 Figure E 1 EPC 3307 Rear Transition module connectors 113 Figure F 1 Installing...

Page 9: ...able 4 20 Reset trip points 70 Table 4 21 Power consumption 70 Table A 1 First 8 bit DMA controller 73 Table A 2 First interrupt controller 73 Table A 3 PCI arbiter control 73 Table A 4 Time counter functions 74 Table A 5 Keyboard controller 74 Table A 6 Real time clock 74 Table A 7 POST checkpoint 74 Table A 8 DMA page registers Intel EX 82371EB of PC AT 75 Table A 9 Port A 75 Table A 10 VGA cont...

Page 10: ...MC to RTM s PIM connector 96 Table C 10 J21 pinout 32 bit local PCI 97 Table C 11 J22 pinout 32 bit local PCI 98 Table C 12 J24 pinout rear I O configuration 99 Table C 13 Primary IDE connector 100 Table C 14 J9 connector A Blue Heron memory card 101 Table C 15 Connector A Blue Heron memory card 102 Table C 16 J8 connector B Blue Heron memory card 103 Table C 17 Connector B Blue Heron memory card ...

Page 11: ...EPC 3307 Hardware Reference x Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 12: ... in BIOS setup menus 4 Theory of operation Describes how EPC 3307 components provide a CompactPCI bus compatible embedded computer with standard PC peripherals and a PCI and ISA interfaces A Chipset and I O map Maps the addresses used for I O and by the chipset registers B Interrupts Lists DMA channel and IRQ assignments to the peripherals supported by the EPC 3307 C Connectors Details the locatio...

Page 13: ...variety of PMC modules such as SVGA LAN adapter or WAN adapters It offers a choice of three memory configurations to address different needs up to 512 MB For more information about the EPC 3306 see the RadiSys web site Notes indicate important information about the product Tips indicate other techniques or procedures you can use to save time or understand the product The globe indicates a World Wi...

Page 14: ... EPC 3307 includes these subsystems The EPC 3307 requires a backplane that supports the CompactPCI Specification Revision 2 1 and the pinouts detailed in Table E 2 Backplane connector J3 and Table E 3 Backplane connector J5 Figure 1 1 The EPC 3307 CPU board A single slot system controller which plugs into a 6U System Slot of a CompactPCI system Rear Transition module A rear I O transition module w...

Page 15: ...or Runs at 700 MHz and includes a 100 MHz Front Side Bus plus a 256kbyte on die cache GX North Bridge Includes a 100 MHz memory bus and a 33MHz 32 bit local PCI bus It supports 256 Mbit SDRAMS but does not use the AGP Graphics port Intel South Bridge PIIX4E chip This PCI to ISA bridge includes two independent EIDE channesl and battery backed real time clock 64 bit CompactPCI interface Located on J...

Page 16: ... that support EIDE 10 100BASE T PIM S17E 1MByte Boot Block Flash memory Onboard headers for Floppy ITP Mouse keyboard RadiSys manufacturing header Port 80 header CPLD JTAG National Semiconductor 87309 Super I O Front panel interface LEDs Blue HS LED and User IPMI controllable Red Green LEDProgrammable RJ45 connectors one each for COM 1 and Ethernet 1 build time option Reset button Watchdog timer w...

Page 17: ...tPCI standard was developed by a consortium of manufacturers known as the PCI Industrial Computer Manufacturers Group PICMG Specifications For more information about PICMG and the CompactPCI standard consult the PICMG website at this URL http www picmg org Table 1 1 EPC 3307 environmental specifications Characteristic State Value Mechanical Dimensions 160 0 mm x 233 35 mm Board thickness 1 6 mm He...

Page 18: ...in per sweep cycle EMC Radiated emissions EMC 3 Operating Designed and tested to pass not certified EN 55022 1998 Class B Immunity ESD 3 Operating Designed and tested to pass not certified All performance criteria from IEC 1000 4 2 EN61000 4 2 1995 4KV direct contact performance criteria B 6KV direct contact performance criteria C 4KV air discharge performance criteria B 8KV air discharge performa...

Page 19: ...EPC 3307 Hardware Reference 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 20: ...PC 3307 10 Replacing the battery 10 Avoid causing ESD electrostatic discharge damage Remove modules from their antistatic bags only in a static free environment Perform the installation process described later in this chapter only in a static free environment During external cable installation ensure that the cables are not active The EPC 3307 is not designed for hot insertion of any interface The...

Page 21: ... labeled from the point of view of looking at the front of the connector Figure 2 1 EPC 3307 CPU board jumper locations Flash Battery MFG Figure 2 2 Flash header settings Pins 1 and 2 Force BIOS Recovery Pins 4 and 5 Boot Block Enable 1 10 1 10 2 9 2 9 Function Pins Description Force BIOS Recovery 1 2 To force recovery of the BIOS connect pin 1 FRC_RCVR to pin 2 GND This signal is connected to the...

Page 22: ...he retaining screws in the top and bottom of the front panel to ensure proper connector mating and prevent the module from loosening due to vibration Boot Block Enable 4 5 To enable re programming of the Boot Block connect pin 5 BBEN to pin 4 VCC The BBEN pins are separated to prevent accidental connections of these pins i e they cannot be easily jumpered together The Boot Block is typically NEVER...

Page 23: ...EPC 3307 disengages from the rear connector 3 Slide the EPC 3307 out of the CompactPCI chassis and place it in the anti static bag that it came in Replacing the battery 1 Before you begin write down all the CMOS setup parameters while the battery is still good or save them using the CMOS save and restore feature of the BIOS configuration as described in the Exit menu on page 41 2 Turn off the powe...

Page 24: ... Restore the CMOS settings as described in the CMOS Save and Restore sub menu on page 43 Battery There is danger of explosion if battery is incorrectly replaced Replace only with same or equivalent type recommended by RadiSys Dispose of used batteries according to manufacturer s instructions After replacing the battery you may need to reset the system clock Artisan Technology Group Quality Instrum...

Page 25: ...EPC 3307 Hardware Reference 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 26: ...ssages Pressing the Escape key during POST displays the Boot First pop up menu after POST completes You can use this menu to override for only this boot the boot options This menu includes the same options as the Boot Menu s top level For information about the options see Boot menu on page 40 BIOS setup screens The EPC 3307 s BIOS includes a setup program that displays and modifies the system conf...

Page 27: ...figuration sub menu Cache Memory sub menu Boot menu None Exit menu CMOS Save and Restore sub menu To Do Display a menu Press the left or right cursor arrow keys and press the Enter key If you use the arrow keys to leave a menu and then return your active field is always at the beginning of the menu Display a submenu fields with a triangle at left Move the cursor to a field with a triangle and pres...

Page 28: ...3 Legacy Diskette B Disabled Primary Master None Primary Slave None Secondary Master None Secondary Slave None Keyboard Features UBE Shadow Control System Memory 640 KB Extended Memory 31744 KB Advanced Boot Exit PhoenixBIOS Setup Utility Main Tab Shift Tab or Enter selects field Item Specific Help Field Description System Time System Date Sets the system time and date To change these values go to...

Page 29: ... enter information for the Master IDE drive connected to the secondary IDE controller For more information see Primary Secondary Master Slave sub menus on page 16 Secondary Slave sub menu Displays a menu that you use to enter information for the Master IDE drive connected to the secondary IDE controller For more information see Primary Secondary Master Slave sub menus on page 16 Boot Options sub m...

Page 30: ...ption for the Type field then enter the specific cylinder head and sector information listed on the label attached to the drive at the factory Figure 3 2 Primary Secondary Master Slave sub menus Main F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Save and Exit PhoenixBIOS Setup Utility Main Tab Shift Tab or Enter selects field Item Specific Help ...

Page 31: ...nished press the ESC key to return to the Main Setup menu Cylinders Specifies the number of cylinders on this system You can specify a number from 1 to 16 Note You can edit this field only when the Type field contains a value of User Heads Specifies the number of heads on this system Note You can edit this field only when the Type field contains a value of User Sectors Specifies the number of sect...

Page 32: ...nfigured and the operating system support Logical Block Addressing LBA Autotyping may change this value if the hard disk reports that it supports LBA You can select one of these Disabled default if no drive is installed Reference hard disk data using the Cylinders Heads Sectors CHS method Enabled default if a drive is installed Reference hard disk data as logical blocks 32 bit I O Determines how t...

Page 33: ...alue depending on the transfer modes that the hard disk reports it supports The fast DMA modes take full advantage of the onboard bus mastering hard disk controller and should yield the highest performance when used in conjunction with multitasking operating systems that support it Ultra DMA Mode Selects the Ultra DMA Mode that the System BIOS uses to access the hard disk You can select one of the...

Page 34: ... delay 1 2 sec Keyboard Features Field Description Numlock Determines whether the keypad keys the Numlock feature operates You can select one of these Auto default Engages the Numlock feature at boot Off Disengages the Numlock feature at boot On Engages the Numlock feature at boot Key Click Determines whether the keyboard produces an audible click each time a key is pressed You can select one of t...

Page 35: ...ese 30 sec default 26 7 sec 21 8 sec 18 5 sec 13 3 sec 10 sec 6 sec 2 sec Keyboard auto repeat delay Sets the delay between when a key is pressed and when the auto repeat feature begins You can select one of these sec sec default sec 1 sec Field Description Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 36: ...B in size Multiple shadow regions may have to be enabled if the BIOS extension to be shadowed is larger than 16KB Figure 3 4 UBE Shadow Control sub menu Main F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Save and Exit PhoenixBIOS Setup Utility Main Tab Shift Tab or Enter selects field Item Specific Help BIOS Extension Source Offset 1C000h Shadow...

Page 37: ...tension in shadow memory You can select one of these D0000h D8000h D2000h DA000h D4000h DC000h D6000h default DE000h Note This field displays only if the BIOS Extension Source field contains a value other than Disabled BIOS Extension Size Size of the extension in increments of 8KBytes You can select one of these 8KB default 40KB 16KB 48KB 24KB 56KB 32KB 64KB Note This field displays only if the BI...

Page 38: ...cy USB Support Disabled Large Disk Access Mode Other Local Bus IDE adapter Both Advanced Chipset Control Main Boot Exit PhoenixBIOS Setup Utility Advanced Tab Shift Tab or Enter selects field Item Specific Help Field Description BIOS Reboot Determines the reboot type You can select one of these Warm Start default The system performs an abbreviated reboot and preserves DRAM memory contents Cold Sta...

Page 39: ...lays a menu that you use to control the use of the CPU cache For more information see Cache Memory sub menu on page 34 Quick Boot Mode Determines which tests run during boot Disabled default Runs all tests Select this option to ensure a robust boot Enabled Skips some tests Select this option to boot more quickly Installed OS Identifies the OS you plan to use on this system Identifying the OS deter...

Page 40: ... mouse and you use it with an OS that does not have USB drivers This option reduces system performance due to frequent SMI interrupts see note below Disabled The system does not support the Legacy USB USB is still functional during POST it is disabled at INT19 Boot Time Note USB is implemented using SMIs and if enabled consumes CPU IRQ and memory resources Many current OSs such as Windows 98 or Wi...

Page 41: ...ne of these Both default Disabled Primary Secondary Advanced Chipset Control sub menu Displays a menu that you use to control chip behavior For more information see Advanced Chipset Control sub menu on page 39 Field Description Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 42: ...ab Shift Tab or Enter selects field Item Specific Help Field Description COM Port Address Specifies the serial port to use for console redirection You can select one of these On board COM A default The system uses COM A for redirection On board COM B The system uses COM B for redirection Disabled The system does not redirect input Baud Rate Specifies the baud rate at which the COM port operates Yo...

Page 43: ...t default Connects the console directly to the system Via modem Connects the console to the system via a modem Continue C R after POST Determines whether console redirection occurs You can select one of these Off default Console redirection stops after the OS loads On Console redirection continues after the OS loads Field Description Artisan Technology Group Quality Instrumentation Guaranteed 888 ...

Page 44: ...Serial port B Enabled Mode Normal Base I O address 2F8 Interrupt IRQ 3 Floppy disk controller Enabled Base I O address Primary I O Device Configuration Advanced Field Description Serial Port A Serial Port B Configures the selected serial port You can select one of these Enabled default The user configures the serial port Auto Either the BIOS or OS configures the serial port Disabled The serial por...

Page 45: ...ou can select one of these IRQ3 default Port B IRQ4 default Port A Note This field displays only if the Serial Port field contains a value of Enabled Floppy Disk Controller Determines whether the floppy disk controller is available for use You can select one of these Enabled default User configuration Disabled No configuration Auto Either the BIOS or OS configures the floppy disk Base I O Address ...

Page 46: ...ect PCI IRQ line B Auto Select PCI IRQ line C Auto Select PCI IRQ line D Auto Select PCI Configuration Advanced Field Description ISA graphics device installed Specifies whether an ISA graphics device is installed in the system No default No ISA graphics device exists in this system Yes An ISA graphics device exists in this system PCI IRQ Line A D Determines which IRQ is used by PCI IRQ PIRQ 1 2 3...

Page 47: ...CFFF Disabled Cache D000 D3FF Disabled Cache D400 D7FF Disabled Cache D800 DBFF Disabled Cache DC00 DFFF Disabled Cache E000 E3FF Write Protect Memory Cache Field Description Memory Cache Determines whether to use L1 and L2 memory caching You can select one of these Enabled default L1 and L2 memory caching occurs Disabled L1 and L2 memory caching does not occur Cache System BIOS Area Determines wh...

Page 48: ...ated Speculative reads are allowed uncached The system does not cache memory Cache Extended Memory Area Determines how the system caches extended memory You can select one of these Write Back default Writes and reads to and from system memory are cached then written to system memory when you perform a write back operation Select this option to reduce bus traffic by eliminating unnecessary writes t...

Page 49: ...ack operation Select this option to reduce bus traffic by eliminating unnecessary writes to system memory This option provides the best performance but requires that all devices that access system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memory are cached Select this option for frame buff...

Page 50: ...s system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memory are cached Select this option for frame buffers or when there are devices on the system bus that access system memory but do not perform snooping of memory accesses Write Protect Reads come from cache lines when possible and read mi...

Page 51: ...us traffic by eliminating unnecessary writes to system memory This option provides the best performance but requires that all devices that access system memory on the system bus be able to snoop memory accesses to ensure system memory and cache coherency Write Through Writes and reads to and from system memory are cached Select this option for frame buffers or when there are devices on the system ...

Page 52: ...S Setup Utility Advanced Tab Shift Tab or Enter selects field Item Specific Help Field Description ECC Config Specifies the error checking method to use when all memory in the system supports ECC x72 You can select one of these ECC default Performs error checking and correction EC Performs only error checking ECC Scrub Performs error checking and correction with scrubbing Disabled No error checkin...

Page 53: ...sts all devices of a specified type available on the system highlight the device type and press the Enter key If more than one device of that type exists use the and keys to change the boot order within the given device type To enable a device highlight the desired device and press the Shift and 1 keys An exclamation point displays to the left of enabled devices To disable a device highlight the d...

Page 54: ...Menu F10 Save and Exit Exit Saving Changes Exit Discarding Changes Load Setup Defaults Discard Changes Save Changes Exit Update BIOS CMOS Save Restore Main Advanced Boot PhoenixBIOS Setup Utility Exit Tab Shift Tab or Enter selects field Item Specific Help Field Description Exit Saving Changes Saves into CMOS the values you just entered and exits the Setup program The new values load and the syste...

Page 55: ...ined BIOS update replacement software from your supplier and reviewed the documentation and procedures provided with that distribution This option changes the flash contents only if the vendor supplied floppy is installed If you select this option by mistake changes made to the BIOS are lost unless already saved using the Save Current Values option The system automatically seaches for the update p...

Page 56: ...tore Condition Determines the conditions under which the BIOS restores CMOS RAM from the FBD when booting You can select one of these Never default CMOS Corruption Always Save CMOS to Flash Immediately saves current settings in the Setup program to CMOS RAM and into the FBD This process may take several seconds to complete Note Always select this option before restoring CMOS from Flash Restore CMO...

Page 57: ...EPC 3307 Hardware Reference 44 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 58: ...nd DOS When reading this file online you can immediately view information about any EPC 3307 topic by placing the mouse cursor over the topic name and clicking For information about Go to this page Organization 44 Block diagram 44 Features 44 CPU module 44 440GX host bridge 47 PIIX4E PCI ISA bridge 48 Intel 21554 PCI PCI bridge 50 H 110 Telephony Interface 52 5 0V PMC site 54 CompactPCI Hot Swap 5...

Page 59: ...che The CPU bus frequency is 100MHz Figure 4 1 EPC 3307 block diagram T8105 TSI BIOS ROM IPMI controller PLD Super I O GX PIII BGA2 Baseboard memory RadiSys memory connector PCIbridge 21554 ENET2 82559 ENET1 82559 PIIX PMC A J24 PMC A J14 PMC A J13 PMC A J11 J12 PMC B J11 J12 IDE conn COM1 J3 FP COM1 J3 MS KB J5 IDE S J5 USB1 2 J3 IDE P J5 or FP build time option J5 64 bit cPCI J1 J1 ISA bus Local...

Page 60: ...hen the chipset is to write within the range of the BIOS Flash boot device As a build time option the main board may have eight pages of Flash at the top of memory Each page is 512k bytes in an 8 bit format One of the pages the PC BIOS page has a boot block architecture The remaining seven pages are made from an Intel Strata Flash The BIOS control Register in the CPLD controls which page is active...

Page 61: ...e The Flash BIOS device is memory addressed and resides in the last 512 KB of system memory at address FFF80000h FFFFFFFFh BIOS ROM and ROM shadowing The EPC 3307 utilizes a Flash Boot Device FBD as its BIOS ROM The BIOS ROM is mapped into the top of the processor s 32 bit address space The BIOS consists of a 16 KByte boot block and the System BIOS in the 96KB Main block and both 8KB parameter blo...

Page 62: ...ns to main memory 440GX PCI bus The Intel 440GX supports CPU to PCI cycles The 440GX and the PCI CLK run at 33 MHz When acting as a PCI target the 440GX does not respond to the cycles listed in the left column of Table 4 1 When acting as a bus master on behalf of the Physical address Device offset FFFFFFFFh FFFFC000h 16 KB BIOS Recovery Code FFFFFh FC000h FFFFBFFFh FFFFA000h 8 KB Parameter Block 2...

Page 63: ...kable to allow two memory cards to be placed onto the main board The following system memory configurations are possible Baseboard memory only 512M Byte w ECC Baseboard 512M module 1G Byte w ECC Baseboard 1G module 1 5G Byte w ECC Baseboard both modules 2 0G Byte w ECC The memory module interface looks exactly like a DIMM It can have a maximum of two memory banks The CPU board uses two 80 pin 0 8m...

Page 64: ...vices through two independent IDE signal channels The IDE interface supports PIO IDE transfers up to 14 MB s and Bus Master IDE transfers up to 33 MB s It does not consume any ISA DMA resources and integrates eight 32 bit buffers for optimal transfers The PIIX4E chip supports Modes 1 2 3 and 4 as well as Bus Master DMA Modes 0 1 and 2 There is no support for the obsolete IDE register at I O addres...

Page 65: ...ler Interface UHCI This includes support that allows legacy software to use a USB based keyboard and mouse When enabled the USB controller uses PIRQD The USB ports are routed to CompactPCI J2 connector SMBus interface and implementation The PIIX4E SMBus interface allows the CPU to communicate via SMBus to other peripherals The SMBus is a subset of the I2C protocol RTC The real time clock RTC Track...

Page 66: ...ist between the host and local subsystems The 21554 configuration space is divided into these parts Primary interface configuration registers Secondary interface configuration registers Device specific configuration registers Both the primary and secondary interface configuration headers contain the 64 byte Type 0 configuration header that corresponds to that interface The device specific configur...

Page 67: ...er action by the Host Reset Control register Primary byte offset DB D8h Secondary byte offset DB D8h Bit Name R W Description 0 Secondary reset R WP Secondary bus reset Possible values include 0 Disabled The 21554 deasserts s_rst_l This bit must be cleared by a configuration write in the case when it is set by a configuration write Otherwise it clears automatically after 100 msec or when p_rst_l d...

Page 68: ...ese sources H 110 Bus on J4 PMC J13 The PMC site on the EPC 3307 is pin compatible with the RadiSys ARTIC 4 port T1 E1 J1 DSP PMC Rear I O is available for the PMC on J14 Table 4 2 T8105 summary Item Description Package 217 pin BGA Power 1 7 Watts max Height 2 33mm max Dim 23mm square Features Local TDM streams H 110 512 Channels Table 4 3 T8105 I O map I O address Reg Description 188h MCR Master ...

Page 69: ...3 48 L_SC2 3 No connect Unused FGA0 J13 52 FGA1 11 No connect Unused Local streams in LDI0 J13 4 LDI1 J13 6 LDI2 J13 10 LDI3 J13 12 LDI4 7 No connect Unused LDI8 J13 16 LDI9 J13 20 LDI10 J13 22 LDI11 J13 26 LDI12 15 No connect Unused Local streams out LDO0 J13 1 LDO1 J13 5 LDO2 J13 7 LDO3 J13 9 LDO4 7 No connect Unused LDO8 J13 13 LDO9 J13 17 LDO10 J13 21 LDO11 J13 23 LDO12 15 No connect Unused Er...

Page 70: ...ster 1 3 CT CLK_SEC 1 Shorts out the 33 ohm termination resistor for CT C8_B and CT FRAMEB Defaults to 33 ohm R s in the circuit Bypass the 33 ohms if the card is the H 110 bus master 1 4 CT RESET 1 Allows Local PCI reset to propagate to the H 110 CT RESET Local PCI reset isolated from H 110 Bus 2 5 T8105 KEEPSEL 1 Enables strong keepers on T8105 H 110 bus signals Undocumented feature of T8105 Def...

Page 71: ...ter in Primary PCI configuration space The register is accessed using the Extended Capabilities Pointer ECP mechanism in PCI configuration space The capability ID for Hot Swap is write able from the serial ROM pre load at PCI configuration space offset ECh to match the industry standard value assigned for Hot Swap the device was designed prior to this assignment In addition to the CompactPCI defin...

Page 72: ...l MAC and PHY interfaces provide support for 10 100BASE T connections Ethernet 1 routes the RX TX pairs to zero ohm resistors that allow for a build time option of either rear Ethernet or front panel Ethernet Ethernet 2 routes its RX TX pair out J5 only The Ethernet controllers use PCI interrupts and REQ GNT signals shown in Table 4 6 The 82559s have a standard PCI 2 1 compliant configuration spac...

Page 73: ...life of 2 years on continuous battery power In a system that is powered on much of the time and where the ambient power off temperature is less than 60 C the battery is estimated to have a life of 10 years Super I O The National PC87309 Super I O controller provides floppy controller parallel port serial port and a keyboard and mouse controller functions It interfaces through the ISA bus and requi...

Page 74: ...board and mouse controller The Super I O provides an integrated keyboard and mouse controller The Super I O keyboard controller located at I O locations 60 64h is functionally equivalent to the industry standard 8042A controller The keyboard interrupt connects to IRQ1 If enabled the mouse interrupt utilizes IRQ12 The keyboard and mouse connectors are located on the RTM For more information about t...

Page 75: ...register which resets to 0 The ISA interface uses an I O address each for data an index register and the kick watchdog bit The base address is 0x0180 and is implemented with PCS1 of the PIIX4 If PCS1 is asserted data can be written into either register or read from the data register Note that the index register is write only The PIIX PCS1 is configured by the BIOS to decode an I O range from 0180 ...

Page 76: ...05 R W Enables disables various interrupts from the CPLD Reset control 0x06 R W Assigns Hard or Soft reset attribute to various reset sources HS latch status and ENUM 0x07 R Allow for software to determine if the HS latch is open or if ENUM is asserted BIOS page select 0x08 R W Selects which BIOS page is accessible Has write protect bit for 7 of the 8 pages CompactPCI features 0x09 R W bit 5 only ...

Page 77: ...UE Determines the blue LED s state 0 zero The LED remains unlit 1 Illuminates the LED G_LED Determines the green LED s state 0 zero The LED remains unlit On a soft reset the Watchdog Central register resets to 0x00 This is the only register in the CPLD other than the Reset Event register affected by a soft reset Table 4 9 Watchdog control register R W Index Default D7 D6 D5 D4 D3 D2 D1 D0 R W 0x01...

Page 78: ...upt control register The EPC 3307 Special Features CPLD controls several interrupts and the CPU INIT signal The Local Interrupt Control register enables or disables these signals The next table defines the bit position to control these features All bits are active high with the exception of the ENUM bit Soft reset value value before soft reset IRQ_7 Enables an interrupt on ENUM from the 21554 draw...

Page 79: ... timer starts in the CPLD If the BIOS fails to write to the KickDog register after four seconds during boot the timer times out and produces a hard reset This prevents a hang condition if the soft reset fails The CPU board can also be reset individually by the host CPU through CompactPCI configuration space Each of the reset sources can be independently configured to generate a soft or a hard rese...

Page 80: ...rom the CPLD SYSEN The SYSEN signal from the CompactPCI backplane This is an active low signal If zero it indicates that the CPU card is plugged into the System Slot of the CompactPCI chassis RTM_P Indicates that a Rear Transition Module is installed It is an active low signal If zero it indicates that the RTM for the CPU is present in the Table 4 14 Hot Swap signals R W Index Default D7 D6 D5 D4 ...

Page 81: ...ts the IPMI H8 microcontroller BIOS bank switching build time option The CPU board has eight pages of Flash at the top of memory Each page is 512k bytes in an 8 bit format The PC BIOS page has a boot block architecture The remaining seven pages are made from an Intel Strata Flash The BIOS control Table 4 16 CompactPCI geographical address Slot number GA4 GA3 GA2 GA1 GA0 0 0 0 0 0 0 1 0 0 0 0 1 2 0...

Page 82: ...write protection of the device The next table shows the page select mapping Soft reset value 0x07 WP Write protects user Flash banks not the PC BIOS Boot block Possible values include 0 Write protects user Flash banks 1 The user may update any of the Flash user banks BC2 0 Selects one of these Flash banks Figure 4 3 BIOS paging PC BIOS 1M 512K User 512K User 512K User 512K User 512K User 512K User...

Page 83: ...ctPCI Specification R3 0 details the board dimensions and maximum component heights on both sides of the board This specification also specifies the location of pin A1 for the J1 and J2 CompactPCI connectors The CPU board dimensions are 160 0 mm x 233 35 mm The CPU board thickness is 1 6 mm The CPU board also contains holes for mounting a solder side cover An ESD strip is provided which complies w...

Page 84: ...ctPCI Specification R3 0 is designed to ensure a flow path across the board The heat sink uses a portion of this space to increase the surface area in the airflow path to improve the heat sink s performance The hard disk drive bracket assembly needs to clear a battery located underneath the assembly On the solder side the maximum component height is 1 92 mm without a solder side cover and 2 29 mm ...

Page 85: ...EPC 3307 Hardware Reference 72 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 86: ...nel 2 address 0005 R W DMA 1 channel 2 count 0006 R W DMA 1 channel 3 address 0007 R W DMA 1 channel 3 count 0008 R W DMA 1 command DMA 1 status 0009 W DMA 1 write request 000A W DMA 1 single mask bit 000B W DMA 1 write mode 000C W DMA 1 clear byte pointer 000D W DMA 1 master clear 000E W DMA 1 clear mask 000F R W DMA 1 read write all mask register bits Table A 2 First interrupt controller I O Add...

Page 87: ...l 0064 Keyboard controller R W Status register Command register Table A 6 Real time clock I O Addr Functional group R W Usage 0070 Real time clock NMI W RTC index register bits 6 0 NMI enable bit 7 0071 R W RTC data register 0 seconds 1 seconds alarm 2 minutes 3 minutes alarm 4 hours 5 hours alarm 6 day of week 7 date of month 8 month 9 year A status A B status B C status C D status D E 3F NVRAM T...

Page 88: ...gister 008C R W DMA page reserved 008D R W DMA page reserved 008E R W DMA page reserved 008F R W DMA low page register refresh Table A 9 Port A I O Addr Functional group R W Usage 0092 Port A R W Fast A20 and reset control Table A 10 VGA controller I O Addr Functional group R W Usage x094 VGA controller R W POS102 access control Table A 11 Second interrupt controller I O Addr Functional group R W ...

Page 89: ...2 write mode 00D8 W DMA 2 clear byte pointer 00DA W DMA 2 master clear 00DC W DMA 2 clear mask 00DE R W DMA 2 read write all register mask bits Table A 14 Coprocessor interface I O Addr Functional group R W Usage 00F0 Coprocessor W Coprocessor error Table A 15 VGA controller I O Addr Functional group R W Usage x102 VGA controller R W POS102 register Table A 16 Secondary IDE I O Addr Functional gro...

Page 90: ...low 01F5 R W Cylinder high 01F6 R W Drive head 01F7 R W Status command Table A 19 ISA Plug and Play I O Addr Functional group R W Usage x279 ISA Plug and Play R W Undocumented source Table A 20 EGA I O Addr Functional group R W Usage x2B0 x2DF EGA R W For compatibility reasons Table A 21 Serial I O COM 4 port I O Addr Functional group R W Usage 02E8 02EF COM 4 serial port R W COM 2 moved to COM 4 ...

Page 91: ...76 R W Alt status device control Table A 24 Parallel I O LPT1 port I O Addr Functional group R W Usage x378 LPT1 parallel port R W Printer data register x379 R W Printer status register Printer status register EPP only x37A R W Printer control register Table A 25 EPP port I O Addr Functional group R W Usage x37B EPP R W EPP address port x37C R W EPP data port 0 x37D R W EPP data port 1 x37E R W EP...

Page 92: ...ontroller data Table A 28 CGA controller I O Addr Functional group R W Usage x3D4 CGA controller R W CRT controller index color x3D5 R W CRT controller data color x3DA R W Input status register 1 color Feature control color Table A 29 COM 3 serial poert I O Addr Functional group R W Usage x3E8 x3EF COM 3 serial port R W COM 1 moved to COM 3 see register description in Table A 32 Serial I O COM 1 p...

Page 93: ...rupt ID register FIFO control register x3FB R W Line control register x3FC R W Modem control register x3FD R Line status register x3FE R W Modem status register Table A 33 Interrupts I O Addr Functional group R W Usage 04D0 Interrupts R W INT1 Edge level control 04D1 R W INT2 Edge level control Table A 34 ECP registers I O Addr Functional group R W Usage x778 ECP registers R W FIFO x779 R W Config...

Page 94: ...GX configuration address register R W Configuration address register Table A 37 PIIX4E I O Addr Functional group R W Usage 0CF9 PIIX4E R W Turbo reset control register Table A 38 443BX configuration data register I O Addr Functional group R W Usage 0CFC 0CFF DWORD only 443GX configuration data register1 R W Configuration data register Artisan Technology Group Quality Instrumentation Guaranteed 888...

Page 95: ...EPC 3307 Hardware Reference 82 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 96: ...t Swap latch is open IRQ12 PS 2 mouse if enabled IRQ13 Numeric coprocessor FERR internal PIIX4E connection IRQ14 Primary IDE IRQ15 Secondary IDE NMI PIIX4E when SERR or IOCHK is asserted software controlled SMI Power management PIRQA PMCA PMCB 21554 bridge PIRQB PMCA PMCB PIRQC PMCA PMCB ENET1 PIRQD PMCA PMCB ENET2 PIIX Note that PIRQ A D correspond directly to the PCI interrupts INT A D The softw...

Page 97: ...EPC 3307 Hardware Reference 84 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 98: ...TM see Appendix E Rear Transition module RTM For information about Go to this page Connector locations 86 CompactPCI connectors 87 J1 connector 87 J2 connector 88 J3 connector 90 J4 connector 91 J5 connector 92 PMC A connectors 93 J11 connector 93 J12 connector 94 J13 connector 95 J14 connector 96 PMC B connectors 97 J21 connector 97 J22 connector 98 IDE primary 100 Memory card connectors 101 J9 1...

Page 99: ...gs see Chapter 2 Configuration and installation Figure C 1 EPC 3307 Main board connectors Reset switch Ethernet optional J5 RS 232 serial port COM 1 Swap ready LED J3 J4 J2 J1 PMC B connectors PMC A connectors User configurable LED Memory card connectors J12 J14 J11 J13 J22 J24 J21 IDE primary J8 J9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 100: ... GND 7 AD 30 AD 29 AD 28 GND AD 27 GND 8 AD 26 GND V I O AD 25 AD 24 GND 9 C BE 3 IDSEL AD 23 GND AD 22 GND 10 AD 21 GND 3 3V AD 20 AD 19 GND 11 AD 18 AD 17 AD 16 GND C BE 2 GND 12 14 Key Area 15 3 3V FRAME IRDY BD_SEL7 TRDY GND 16 DEVSEL GND V I O 2 6 STOP LOCK GND 17 3 3V IPMB_CLK IPMB_DAT GND PERR GND 18 SERR GND 3 3V PAR C BE 1 GND 19 3 3V AD 15 AD 14 GND AD 13 GND 20 AD 12 GND V I O 2 AD 11 A...

Page 101: ...or P2 are also implemented only on the System Slot board C15 C16 D17 E15 E17 A19 A21 B19 B20 and B21 Table C 2 CompactPCI J2 connector Pin A B C D E F8 13 RSV GND RSV RSV RSV GND 23 RSV RSV UNC 4 RSV RSV GND 33 RSV GND RSV RSV RSV GND 4 V I O BRSV C BE 7 GND C BE 6 GND 5 C BE 5 GND V I O 2 C BE 4 PAR64 GND 6 AD 63 AD 62 AD 61 GND AD 60 GND 7 AD 59 GND V I O 2 AD 58 AD 57 GND 8 AD 56 AD 55 AD 54 GN...

Page 102: ... 8 Observation Some manufacturers of top shields utilize every other ground pin while some use every ground pin Note Shield connections mate at approximately the same timer as medium length pins 9 CompactPCI connector pin numbering is intentionally different from the connector manufacturer s pin numbering This was done to allow the connectors to start at the bottom of the board and grow upward fro...

Page 103: ...CBIO43 PMCBIO42 PMCBIO41 GND 6 PMCBIO40 PMCBIO39 PMCBIO38 PMCBIO37 PMCBIO36 GND 7 PMCBIO35 PMCBIO34 PMCBIO33 PMCBIO32 PMCBIO31 GND 8 PMCBIO30 PMCBIO29 PMCBIO28 PMCBIO27 PMCBIO26 GND 9 PMCBIO25 PMCBIO24 PMCBIO23 PMCBIO22 PMCBIO21 GND 10 PMCBIO20 PMCBIO19 PMCBIO18 PMCBIO17 PMCBIO16 GND 11 PMCBIO15 PMCBIO14 PMCBIO13 PMCBIO12 PMCBIO11 GND 12 PMCBIO10 PMCBIO9 PMCBIO8 PMCBIO7 PMCBIO6 GND 13 PMCBIO5 PMCB...

Page 104: ..._D0 3 3V CT_D1 CT_D2 CT_D3 GND 2 CT_D4 CT_D5 CT_D6 CT_D7 GND GND 3 CT_D8 CT_D9 CT_D10 GND SCLKx2 GND 4 CT_D11 5V CT_D12 3 3V SCLK GND 5 CT_D13 CT_D14 CT_D15 3 3V CT_NETREF2GND 6 CT_D16 CT_D17 CT_D18 GND CT_NETREF1GND 7 CT_D19 5V CT_D20 GND CT_C8_B GND 8 CT_D21 CT_D22 CT_D23 5V CT_C8_A GND 9 CT_D24 CT_D25 CT_D26 GND FR_COMP GND 10 CT_D27 3 3V CT_D28 5V CT_FRAME_BGND 11 CT_D29 CT_D30 CT_D31 CT_VIO C...

Page 105: ...3 PMCAIO32 PMCAIO31 GND 8 PMCAIO30 PMCAIO29 PMCAIO28 PMCAIO27 PMCAIO26 GND 9 PMCAIO25 PMCAIO24 PMCAIO23 PMCAIO22 PMCAIO21 GND 10 PMCAIO20 PMCAIO19 PMCAIO18 PMCAIO17 PMCAIO16 GND 11 PMCAIO15 PMCAIO14 PMCAIO13 PMCAIO12 PMCAIO11 GND 12 PMCAIO10 PMCAIO9 PMCAIO8 PMCAIO7 PMCAIO6 GND 13 PMCAIO5 PMCAIO4 PMCAIO3 PMCAIO2 PMCAIO1 GND 14 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 GND 15 IDE_D5 IDE_D6 IDE_D7 IDE_D8 ID...

Page 106: ...5 GND 26 LPCI C BE 3 27 LPCI AD 22 28 LPCI AD 21 29 LPCI AD 19 30 VCC 31 V I O 3 3V 32 LPCI AD 17 33 LPCI FRAME 34 GND 35 GND 36 LPCI IRDY 37 LPCI DEVSEL 38 VCC 39 GND 40 LPCI LOCK 41 LPCI SDONE 42 LPCI SBO 43 LPCI PAR 44 GND 45 V I O 3 3V 46 LPCI AD 15 47 LPCI AD 12 48 LPCI AD 11 49 LPCI AD 09 50 VCC 51 GND 52 LPCI C BE 0 53 LPCI AD 06 54 LPCI AD 05 55 LPCI AD 04 56 GND 57 V I O 3 3V 58 LPCI AD 0...

Page 107: ...23 LPCI AD 24 24 3 3V 25 PMCA IDSEL 26 LPCI AD 23 27 3 3V 28 LPCI AD 20 29 LPCI AD 18 30 GND 31 LPCI AD 16 32 LPCI C BE 2 33 GND 34 No connect 35 LPCI TRDY 36 3 3V 37 GND 38 LPCI STOP 39 LPCI PERR 40 GND 41 3 3V 42 LPCI SERR 43 LPCI C BE 1 44 GND 45 LPCI AD 14 46 LPCI AD 13 47 GND 48 LPCI AD 10 49 LPCI AD 080 50 3 3V 51 LPCI AD 07 52 No connect 53 3 3V 54 No connect 55 No connect 56 GND 57 No conn...

Page 108: ...I 11 27 No connect 28 No connect 29 TDM L_REF 0 30 No connect 31 No connect 32 No connect 33 No connect 34 GND 35 No connect 36 No connect 37 TDM L_REF 1 38 No connect 39 GND 40 No connect 41 No connect 42 No connect 43 TDM L_REF 2 44 No connect 45 No connect 46 No connect 47 No connect 48 TDM L_SC 1 49 TDM L_REF 3 50 No connect 51 GND 52 TDM FBG 0 53 No connect 54 No connect 55 No connect 56 GND ...

Page 109: ...09 23 J5 C09 24 J5 B09 25 J5 A09 26 J5 E08 27 J5 D08 28 J5 C08 29 J5 B08 30 J5 A08 31 J5 E07 32 J5 D07 33 J5 C07 34 J5 B07 35 J5 A07 36 J5 E06 37 J5 D06 38 J5 C06 39 J5 B06 40 J5 A06 41 J5 E05 42 J5 D05 43 J5 C05 44 J5 B05 45 J5 A05 46 J5 E04 47 J5 D04 48 J5 C04 49 J5 B04 50 J5 A04 51 J5 E03 52 J5 D03 53 J5 C03 54 J5 B03 55 J5 A03 56 J5 E02 57 J5 D02 58 J5 C02 59 J5 B02 60 J5 A02 61 J5 E01 62 J5 D...

Page 110: ...25 GND 26 LPCI C BE 3 27 LPCI AD 22 28 LPCI AD 21 29 LPCI AD 19 30 VCC 31 V I O 3 3V 32 LPCI AD 17 33 LPCI FRAME 34 GND 35 GND 36 LPCI IRDY 37 LPCI DEVSEL 38 VCC 39 GND 40 LPCI LOCK 41 LPCI SDONE 42 LPCI SBO 43 LPCI PAR 44 GND 45 V I O 3 3V 46 LPCI AD 15 47 LPCI AD 12 48 LPCI AD 11 49 LPCI AD 09 50 VCC 51 GND 52 LPCI C BE 0 53 LPCI AD 06 54 LPCI AD 05 55 LPCI AD 04 56 GND 57 V I O 3 3V 58 LPCI AD ...

Page 111: ...23 LPCI AD 24 24 3 3V 25 PMCA IDSEL 26 LPCI AD 23 27 3 3V 28 LPCI AD 20 29 LPCI AD 18 30 GND 31 LPCI AD 16 32 LPCI C BE 2 33 GND 34 No connect 35 LPCI TRDY 36 3 3V 37 GND 38 LPCI STOP 39 LPCI PERR 40 GND 41 3 3V 42 LPCI SERR 43 LPCI C BE 1 44 GND 45 LPCI AD 14 46 LPCI AD 13 47 GND 48 LPCI AD 10 49 LPCI AD 080 50 3 3V 51 LPCI AD 07 52 No connect 53 3 3V 54 No connect 55 No connect 56 GND 57 No conn...

Page 112: ... B13 5 J3 A13 6 J3 E12 7 J3 D12 8 J3 C12 9 J3 B12 10 J3 A12 11 J3 E11 12 J3 D11 13 J3 C11 14 J3 B11 15 J3 A11 16 J3 E10 17 J3 D10 18 J3 C10 19 J3 B10 20 J3 A10 21 J3 E09 22 J3 D09 23 J3 C09 24 J3 B09 25 J3 A09 26 J3 E08 27 J3 D08 28 J3 C08 29 J3 B08 30 J3 A08 31 J3 E07 32 J3 D07 33 J3 C07 34 J3 B07 35 J3 A07 36 J3 E06 37 J3 D06 38 J3 C06 39 J3 B06 40 J3 A06 41 J3 E05 42 J3 D05 43 J3 C05 44 J3 B05 ...

Page 113: ... 8 IDE D10 9 IDE D4 10 IDE D11 11 IDE D3 12 IDE D12 13 IDE D2 14 IDE D13 15 IDE D1 16 IDE D14 17 IDE D0 18 IDE D15 19 IDE GND 20 No connect 21 IDE DRQ 22 GND 23 IDE IOW 24 GND 25 IDE IOR 26 GND 27 IDE IORDY 28 No connect 29 IDE DAK 30 GND 31 IDE IRQ 32 No connect 33 IDE A1 34 No connect 35 IDE A0 36 IDE A2 37 IDE CS1 38 IDE CS3 39 No connect 40 GND 41 5V 42 5V 43 GND 44 No connect 44 2 1 43 Artisa...

Page 114: ...DQ39 21 3 3V 22 GND 23 DQ8 24 DQ40 25 DQ9 26 DQ41 27 DQ10 28 DQ42 29 DQ11 30 DQ43 31 3 3V 32 GND 33 DQ12 34 DQ44 35 DQ13 36 DQ45 37 DQ14 38 DQ46 39 DQ15 40 DQ47 41 3 3V 42 GND 43 ECC0 44 ECC2 45 ECC1 46 CC3 47 GND 48 GND 49 CLK_LWR 50 GND 51 GND 52 GND 53 CLK_UPR 54 GND 55 GND 56 GND 57 A0 58 A1 59 A2 60 A3 61 A4 62 A5 63 A6 64 A7 65 3 3V 66 GND 67 A8 68 A9 80 2 1 79 Artisan Technology Group Quali...

Page 115: ...A Blue Heron memory card Pin Signal Pin Signal 69 A10 70 A11 71 BA0 A12 72 BA1 A13 73 A12 A14 74 GND 75 3 3V 76 GND 77 CKE0_LWR 78 CKE1_LWR 79 CKE0_UPR 80 CKE1_UPR Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 116: ...GND 23 DQ16 24 DQ48 25 DQ17 26 DQ49 27 DQ18 28 DQ50 29 DQ19 30 DQ51 31 3 3V 32 GND 33 DQ20 34 DQ52 35 DQ21 36 DQ53 37 DQ22 38 DQ54 39 DQ23 40 DQ55 41 3 3V 42 GND 43 DQ24 44 DQ56 45 DQ25 46 DQ57 47 DQ26 48 DQ58 49 DQ27 50 DQ59 51 3 3V 52 GND 53 DQ28 54 DQ60 55 DQ29 56 DQ61 57 DQ30 58 DQ62 59 DQ31 60 DQ63 61 3 3V 62 GND 63 ECC4 64 ECC6 65 ECC5 66 ECC7 67 3 3V 68 GND 80 2 1 79 Artisan Technology Grou...

Page 117: ...PR 78 SA1_UPR 79 3 3V 80 GND Table C 18 RJ45 phone jack pin out Pin Signal Pin Signal 1 Transmit 5 Center tap transmit 2 Transmit 6 Receive 3 Receive 7 Center tap receive 4 Center tap transmit 8 Center tap receive 1 2 3 4 5 6 7 8 Table C 19 RJ45 phone jack pin out Pin Signal Pin Signal 1 Data carrier detect IN CD 5 Receive data IN RxD 2 Request to send OUT RTS6 Signal ground 3 Signal ground 7 Clea...

Page 118: ...afe to eject the CPU board The ejector handle switch must be activated first then after the OS has been notified the OS illuminates the LED indicating it is safe to pull the CPU board out from the chassis User configurable Red green You can configure this dual color LED to indicate an event of your choosing For information about configuring these LEDs see Front panel red green LED on page 64 You c...

Page 119: ...EPC 3307 Hardware Reference 106 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 120: ...ot set correctly 3 Timer error System timer 0 failed 4 Diskette error Floppy type does not match setup 5 I O chip error I O conflicts exist for serial and parallel ports floppy hard disk any or all 6 Other error IRQ conflict unsupported COM port configuration keyboard locked Pentium cooling fan has failed The System BIOS prints an error message but does not halt when it encounters the following er...

Page 121: ...EPC 3307 Hardware Reference 108 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 122: ...clicking Features The RTM includes Two Ethernet 10 100BASE TX RJ 45 connectors via the backplane J5 connector interface A PC compatible RS 232 serial port 16550C Compatible via the backplane J3 connector PS 2 style keyboard and mouse connectors A USB connector PIM PMC I O module connector For information about Go to this page Features 109 Block diagram 110 Installing and configuring the RTM 111 Co...

Page 123: ...nnectors to the rear panel connectors Ethernet 2x Serial Mouse Keyboard USB Table E 1 EPC 3307 Rear Transition module block diagram PMC REAR I O ENET 1 RJ45 J5 J3 PIM ENET 2 RJ45 KBD M RST SW USB 1 COM2 DB9 SEC IDE USB 2 COM 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 124: ...ector pinouts see Appendix C Connectors 6 Complete remaining steps as required Typical remaining steps include BIOS configuration For information about setting up the BIOS configuration see Chapter 3 BIOS configuration Driver software installation Application software installation Your system may be preconfigured by your supplier or you may be required to perform these tasks yourself For informati...

Page 125: ...of the extractors inward until the extractor handle swings out and pivots freely 2 Pull outward on the extractor handles until the RTM disengages from the rear connector 3 Slide the RTM out of the CompactPCI chassis When finished with the tasks at hand follow the instructions in Inserting the RTM on page 111 to re install the RTM Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S...

Page 126: ...TM For information about Go to this page Connector locations 113 Backplane J3 114 Backplane J5 115 Ethernet 115 COM 1 header 116 COM 2 116 IDE secondary 117 Keyboard mouse 117 USB 120 Figure E 1 EPC 3307 Rear Transition module connectors Keyboard mouse Ethernet COM 2 Backplane J5 Backplane J3 IDE secondary PIM PMC I O module COM 1 header USB Artisan Technology Group Quality Instrumentation Guarant...

Page 127: ...IO42 PMCBIO41 GND 6 PMCBIO40 PMCBIO39 PMCBIO38 PMCBIO37 PMCBIO36 GND 7 PMCBIO35 PMCBIO34 PMCBIO33 PMCBIO32 PMCBIO31 GND 8 PMCBIO30 PMCBIO29 PMCBIO28 PMCBIO27 PMCBIO26 GND 9 PMCBIO25 PMCBIO24 PMCBIO23 PMCBIO22 PMCBIO21 GND 10 PMCBIO20 PMCBIO19 PMCBIO18 PMCBIO17 PMCBIO16 GND 11 PMCBIO15 PMCBIO14 PMCBIO13 PMCBIO12 PMCBIO11 GND 12 PMCBIO10 PMCBIO9 PMCBIO8 PMCBIO7 PMCBIO6 GND 13 PMCBIO5 PMCBIO4 PMCBIO3...

Page 128: ... 8 PMCAIO30 PMCAIO29 PMCAIO28 PMCAIO27 PMCAIO26 GND 9 PMCAIO25 PMCAIO24 PMCAIO23 PMCAIO22 PMCAIO21 GND 10 PMCAIO20 PMCAIO19 PMCAIO18 PMCAIO17 PMCAIO16 GND 11 PMCAIO15 PMCAIO14 PMCAIO13 PMCAIO12 PMCAIO11 GND 12 PMCAIO10 PMCAIO9 PMCAIO8 PMCAIO7 PMCAIO6 GND 13 PMCAIO5 PMCAIO4 PMCAIO3 PMCAIO2 PMCAIO1 GND 14 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 GND 15 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 GND 16 IDE_D10 IDE...

Page 129: ... Receive data 7 Request to send 3 Transmit data 8 Clear to send 4 Data terminal ready 9 Ring indicator 5 Signal ground 10 No connect 2 1 10 9 Table E 6 DB 9 COM 2 pin out Pin Signal Pin Signal 1 Carrier detect 6 Data set ready 2 Receive data 7 Request to send 3 Transmit data 8 Clear to send 4 Data terminal ready 9 Ring indicator 5 Signal ground 1 5 6 9 Artisan Technology Group Quality Instrumentat...

Page 130: ... 16 IDE D14 17 IDE D0 18 IDE D15 19 IDE GND 20 No connect 21 IDE DRQ 22 GND 23 IDE IOW 24 GND 25 IDE IOR 26 GND 27 IDE IORDY 28 No connect 29 IDE DAK 30 GND 31 IDE IRQ 32 No connect 33 IDE A1 34 No connect 35 IDE A0 36 IDE A2 37 IDE CS1 38 IDE CS3 39 No connect 40 GND 41 5V 42 5V 43 GND 44 No connect 44 2 1 43 Table E 8 Keyboard mouse pin out Pin Signal Pin Signal 1 Keyboard data 4 5V 2 Mouse data...

Page 131: ... connect 18 GND 19 No connect 20 No connect 21 5V 22 No connect 23 No connect 24 No connect 25 No connect 26 3 3V 27 No connect 28 No connect 29 GND 30 No connect 31 No connect 32 No connect 33 No connect 34 GND 35 No connect 36 No connect 37 5V 38 No connect 39 No connect 40 No connect 41 No connect 42 3 3V 43 No connect 44 No connect 45 GND 46 No connect 47 No connect 48 No connect 49 No connect...

Page 132: ...MC B J24 27 28 PMC B J24 28 29 PMC B J24 29 30 PMC B J24 30 31 PMC B J24 31 32 PMC B J24 32 33 PMC B J24 33 34 PMC B J24 34 35 PMC B J24 35 36 PMC B J24 36 37 PMC B J24 37 38 PMC B J24 38 39 PMC B J24 39 40 PMC B J24 40 41 PMC B J24 41 42 PMC B J24 42 43 PMC B J24 43 44 PMC B J24 44 45 PMC B J24 45 46 PMC B J24 46 47 PMC B J24 47 48 PMC B J24 48 49 PMC B J24 49 50 PMC B J24 50 51 PMC B J24 51 52 P...

Page 133: ...RTM s rear panel is a 4 pin single height connector defined as follows Table E 11 USB connector pin out Pin Signal Mechanical solder lug Shield ground 1 5V 2 DATA 3 DATA 4 Ground Mechanical solder lug Shield ground 1 2 3 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 134: ...F 1 Installing a PMC module 2 1 Avoid causing ESD damage Remove modules from their antistatic bags only in a static free environment Perform the installation process described later in this chapter only in a static free environment During external cable installation ensure that the cables are not active The EPC 3307 is not designed for hot insertion of any interface The EPC 3307 modules like most ...

Page 135: ...optional PMC module you must disassemble the board before performing maintenance or upgrades on the EPC 3307 To separate the PMC module and the main board 1 Remove the EPC 3307 from the CompactPCI chassis as described in Removing the EPC 3307 on page 10 2 Remove screws on the back of the main board 3 Pull the boards apart while keeping them parallel Continue applying force until the connectors com...

Page 136: ... chip 131 Figure G 1 Flash chip configuration Boot block ESCD BIOS Other CSR user extensions BIOS extensions etc Boot block A 16 KB hardware write protected area that contains the Boot Block program This program Completes minimal hardware setup including checking for conditions that require re programming the flash chip Initiates a re flash if conditions warrant When initiating a re flash this pro...

Page 137: ...y drive Force recovery jumper This technique is useful if a keyboard and monitor are not available Use extreme caution when re programming the flash chip The Boot Block rarely changes and should not require re programming Figure G 2 Flash chip re programming coverage Boot block ESCD BIOS Other CSR user extensions BIOS extensions etc BIOS Re programs only BIOS related sections of the flash chip Fla...

Page 138: ...corrupt Figure G 3 Flash chip re programming process flow Create a Flash Boot diskette Done Which re program method Set BIOS configuration options Use the Force Recovery jumper Run phlash exe Re programming the flash chip What part to re program FBD BIOS Download fbdrec zip Download bbrec zip Download biosrec zip Boot Block Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ...

Page 139: ... will perform this type of update rarely if ever Decide which re programming process to use phlash program Use this method to re program the BIOS or FBD from the DOS command line RadiSys recommends this as the method that provides the most feedback during the re programming process BIOS configuration program options Use this method if the existing BIOS runs RadiSys recommends this as the simplest ...

Page 140: ...d to command line prompts Insert a blank formatted 1 44MB floppy diskette into the system drive then complete tasks as prompted by the program Use extreme caution when re programming the Boot Block A BIOS boot block rarely changes and should not require re programming Filename Description readme txt Describes the transmittal and includes instructions and issues that arose too late to include in ot...

Page 141: ...rections for the re flash method you want to use Method Page Using phlash exe to re program the flash chip 129 Using BIOS configuration options to re program the flash chip 130 Using jumpers to re program the flash chip 131 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 142: ...operation A Turn system power off B Locate the BIOS configuration jumper block and disconnect the Boot Block Write Enable pins C Replace the EPC 3307 in the CompactPCI chassis D Power up the EPC 3307 Do not install this jumper unless a Boot Block update is required A BIOS boot block rarely changes and seldom if ever requires re programming 1 10 2 9 Pins 3 and 8 required to re program the Boot Bloc...

Page 143: ...into the floppy drive The phlash exe program automatically runs and re programs the flash chip A Remove the Flash Boot diskette from the drive when the drive stops accessing the disk 4 If you re programmed the Boot Block remove the Boot Block write enable jumper and return the system to normal operation A Turn system power off B Locate the BIOS configuration jumper block and disconnect the Boot Bl...

Page 144: ...he system to normal operation A Turn system power off B Locate the BIOS configuration jumper block and disconnect the Force BIOS Recovery pins and if you connected them the Boot Block Write Enable pins C Replace the EPC 3307 in the CompactPCI chassis D Power up the EPC 3307 1 10 2 9 Pins 5 and 6 required to re program the FBD or BIOS 1 10 2 9 Pins 3 and 8 required to re program the Boot Block Do n...

Page 145: ...EPC 3307 Hardware Reference 132 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 146: ...ically configure the drive controller BIOS Basic Input Output System Firmware in a PC compatible computer that runs when the computer is powered up The BIOS initializes the computer hardware allows the user to configure the hardware boots the operating system and provides standard mechanisms that the operating system can use to access the PC s peripheral devices BDA BIOS Data Area BIOS Data Area A...

Page 147: ...ts that along with a CPU memory and other peripherals implements an IBM PC AT compatible computer The chipset typically implements a DRAM controller bus interface logic and PC peripheral devices CAS Column Address Strobe An input signal from the DRAM controller to an internal DRAM latch register specifying the column at which to read or write data The DRAM requires a column address and a row addre...

Page 148: ...ompared to other erasing methods Error Checking and Correction A feature of the T2 chipset that enables it to detect single or multi bit errors in DRAM reads and correct single bit errors This feature requires that all banks of DRAM use x36 parity SO DIMMs ECP Extended Capabilities Port An enhancement of the standard PC parallel port that allows high speed bi directional data transfers and other f...

Page 149: ...pattern of sleeves on a female header plug h Hexadecimal A base 16 numbering system using numeric symbols 0 through 9 plus alpha characters A B C D E and F as the 16 digit symbols Digits A through F are equivalent to the decimal values 10 through 15 Host Bus The address data bus that connects the CPU and the chipset ISA Industry Standard Architecture A popular microcomputer expansion bus architect...

Page 150: ... the CHS reference method in that the BIOS requires no information relating to disk cylinders heads or sectors LBA can be used only on hard disk drives designed to support it MB or MByte Megabyte Approximately one million bytes 2 20 1 048 576 bytes exactly Memory A designated system area to which data can be stored and from which data can be retrieved A typical computer system has more than one me...

Page 151: ... sense a program is also referred to as a software application which can actually contain many related individual programs PAL Programmable Array Logic A semiconductor programmable ROM which accepts customized logic gate programming to produce a desired sum of products output function RAM Random Access Memory Memory in which the actual physical location of a memory word has no effect on how long i...

Page 152: ... use of half as many pins to define an address location in a DRAM device as would otherwise be required Segment A section or portion of addressable memory serving to hold code data stack or other information allowing more efficient memory usage in a computer system A segment is the portion of a real mode address which specifies the fixed base address to which the offset is applied Serial Port A ph...

Page 153: ...cal connectors but capable of much higher throughput upwards of 12Mbs UED User Editable Drive A feature of the NY1210 s Phoenix NuBIOS When a User type hard disk drive setting shows in the IDE Adapter Sub Menu the BIOS queries the hard disk drive for the purpose of retrieving disk geometry If the hard disk drive is capable of providing this information the BIOS uses it to automatically set up the ...

Page 154: ...ion 134 C cache system BIOS 34 Video BIOS 34 Cache Memory sub menu 34 chipset defined 134 clock TOD 60 CMOS RAM 13 60 COM 1 104 COM2 connector 116 CompactPCI features register 67 geographical address 68 configuration byte defined 134 I O device 26 PCI 26 connectors COM2 116 EIDE primary 100 117 Ethernet 104 115 keyboard 117 mouse 117 RS 232 104 USB 120 console redirection 26 29 39 control PCI arbi...

Page 155: ...ramming described 123 using BIOS options 130 using jumpers 131 using phlash exe 129 floppy disk drives identifying 16 front panel LEDs 64 105 reset switch 105 G geographical address CompactPCI 68 glossary 133 green LED 64 H H1 COM1 jumper 116 hard disk transfer mode 20 header defined 136 help ii Hot Swap LED 105 Hot Swap signals 67 humidity 4 I I O device configuration 26 I O Map addresses 73 DMA ...

Page 156: ...eripherals 10 peripherals connecting 111 phlash exe 127 129 Phoenix NuBIOS 13 I O Map 74 physical address defined 138 PICMG URL 4 platform bin 127 Plug and Play 48 PMC module disconnecting 122 installing 121 port A 75 ports parallel 60 78 serial 60 104 POST 13 138 POST checkpoint 74 power 70 management controller 75 Power On Self Test POST defined 138 Power On Self Test POST 13 primary EIDE connec...

Page 157: ... ii Symmetrically Addressable SIMM defined 140 system BIOS caching 34 memory amount displayed 16 system memory defined 140 T technical support ii temperature 4 time access 133 time counter functions I O map 74 timer watchdog 63 TOD clock 60 transfer mode hard disk 20 troubleshooting ii type disk 18 U UBE Shadow Control Sub Menu 23 UED term defined 140 updates BIOS defined 134 flash defined 136 URL...

Page 158: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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