6.3.2.1 Board Address Test
The board address test is performed by setting SW I and doing a read/write at the proper
address, and verifying the correct response; t h e n doing a read/write a t an incorrect
address and verifying the correct response.
This test is repeated for each bit of SW I. I n the performance o f this test, address lines
LAO through LA14 are tested.
6.3.2.2 Reset Test
This test checks the RSTCLK line and associated hardware. A write/read is performed,
and the 7064 is reset. A read is executed to verify reset has occurred.
6.3.2.3 Output Bit Test
This test performs write/read operations o f the following patterns: A 5 hex, 5 A hex,
walking high, bit and walking low bit pattern.
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