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Smart Module Series

SC606T Series Hardware Design

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Appendix B GPRS Coding Schemes

Table 55: Description of Different Coding Schemes

Scheme

CS-1

CS-2

CS-3

CS-4

Code Rate

1/2

2/3

3/4

USF

Pre-coded USF

Radio Block excl.USF and BCS

181

268

312

428

BCS

Tail

Coded Bits

456

588

676

456

Punctured Bits

132

220

Data Rate Kb/s

9.05

13.4

15.6

21.4

Summary of Contents for SC606T Series

Page 1: ...SC606T Series Hardware Design Smart Module Series Version 1 0 Date 2021 03 16 Status Released ...

Page 2: ...t prior notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under devel...

Page 3: ...on of Quectel Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2021 All rights reserved ...

Page 4: ...vices may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emergen...

Page 5: ...ardware Design SC606T_Series_Hardware_Design 4 116 About the Document Revision History Version Date Author Description 2021 01 25 Dorian MENG Mike ZENG Creation of the document 1 0 2021 03 16 Dorian MENG Mike ZENG First official release ...

Page 6: ...iption 24 3 4 Power Supply 37 3 4 1 Power Supply Pins 37 3 4 2 Decrease Voltage Drop 37 3 4 3 Reference Design for Power Supply 38 3 5 Turn On and Turn Off Timing 39 3 5 1 Turn On Module 39 3 5 2 Turn Off Module 41 3 6 VRTC Interface 41 3 7 Power Output 42 3 8 USB Interface 43 3 9 UART Interfaces 46 3 10 U SIM Interfaces 48 3 11 SD Card Interface 50 3 12 GPIO Interfaces 52 3 13 I2C Interfaces 53 3...

Page 7: ...rsity Antenna Interfaces 81 6 1 2 Reference Designs for RF Layouts 82 6 2 Wi Fi BT and FM Antenna Interfaces 83 6 3 GNSS Antenna Interface 84 6 3 1 Reference Design for Passive Antenna 85 6 3 2 Reference Design for Active Antenna 86 6 4 Antenna Installation 86 6 4 1 Antenna Requirements 86 6 4 2 Recommended RF Connector for Antenna Installation 87 7 Reliability Electrical and Radio Characteristics...

Page 8: ...06T Series Hardware Design SC606T_Series_Hardware_Design 7 116 10 Appendix A References 111 11 Appendix B GPRS Coding Schemes 116 12 Appendix C GPRS Multi slot Classes 117 13 Appendix D EDGE Modulation and Coding Schemes 119 ...

Page 9: ... SPI Interfaces 54 Table 18 Pin Definition of ADC Interface 54 Table 19 Pin Definition of LCM Interfaces 55 Table 20 Pin Definition of Touch Panel Interfaces 58 Table 21 Pin Definition of Camera Interfaces 59 Table 22 MIPI Trace Length Inside the Module 64 Table 23 Pin Definition of Sensor Interfaces 66 Table 24 Pin Definition of Audio Interfaces 67 Table 25 Wi Fi Transmitting Performance 72 Table...

Page 10: ...ble 47 SC606T JP RF Receiving Sensitivity 99 Table 48 SC606T EM RF Receiving Sensitivity 100 Table 49 SC606T NAD RF Receiving Sensitivity 101 Table 50 ESD Characteristics Temperature 25 C Humidity 45 102 Table 51 Recommended Thermal Profile Parameters 109 Table 52 Reel Packaging 110 Table 53 Related Documents 111 Table 54 Terms and Abbreviations 111 Table 55 Description of Different Coding Schemes...

Page 11: ...8 Figure 21 Reference Design for Touch Panel Interface 59 Figure 22 Reference Design for Dual Camera Application 62 Figure 23 Reference Design for Triple Camera Application 63 Figure 24 Reference Design for Analog ECM type Microphone 68 Figure 25 Reference Design for MEMS type Microphone 68 Figure 26 Reference Design for Earpiece Interface 69 Figure 27 Reference Design for Headphone Interface with...

Page 12: ... 42 Top and Side Dimensions Unit mm 103 Figure 43 Bottom Dimensions Perspective View 104 Figure 44 Recommended Footprint Perspective View 105 Figure 45 Top and Bottom Views 106 Figure 46 Recommended Reflow Soldering Thermal Profile 108 Figure 47 Tape Dimensions 110 Figure 48 Reel Dimensions 110 ...

Page 13: ...y The antenna installation and operating configurations of this transmitter including any applicable source based timeaveraging duty factor antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2 1091 2 The EUT is a mobile device maintain at least a 20 cm separation between the EUT and the user s body and must not transmit simultaneously with any other antenna or trans...

Page 14: ...only used methods for access to remove the module so that the FCC ID of the module is visible then an additional permanent label referring to the enclosed module Contains Transmitter Module FCC ID XMR2021SC606TNAD or Contains FCC ID XMR2021SC606TNAD must be used The host OEM user manual must also contain clear instructions on how end users can find and or access the module and the FCC ID The final...

Page 15: ...omettre le fonctionnement Déclaration sur l exposition aux rayonnements RF L autre utilisé pour l émetteur doit être installé pour fournir une distance de séparation d au moins 20 cm de toutes les personnes et ne doit pas être colocalisé ou fonctionner conjointement avec une autre antenne ou un autre émetteur The host product shall be properly labeled to identify the modules within the host produc...

Page 16: ...codecs With the built in high performance AdrenoTM 506 graphics processing unit Provide multiple audio and video input output interfaces as well as abundant GPIO interfaces The series comes in SC606T EM SC606T NAD SC606T JP and SC606T WF models The following tables show the frequency bands CA combinations as well as the Wi Fi Bluetooth and GNSS frequency bands supported by each model Table 1 Frequ...

Page 17: ...TE TDD B41 Intra band 2CA DL 2A 2A 2C 4A 4A 5A 5A 5B 7A 7A 7C 66A 66A 66B 66C 41A 41A 41C WCDMA B2 B4 B5 GSM Wi Fi 802 11a b g n ac 2402 2482 MHz 5180 5825 MHz BT 4 2 LE 2402 2480 MHz GNSS GPS 1575 42 1 023 MHz GLONASS 1597 5 1605 8 MHz BeiDou 1561 098 2 046 MHz Mode Details LTE FDD B1 B3 B5 B8 B11 B18 B19 B21 B26 B28A B28B LTE TDD B41 Intra band 2CA DL 1A 1A 1C 3A 3A 3C 5A 5A 5B 41A 41A 41C WCDMA...

Page 18: ...hone and tablet PC 2 2 Key Features Table 5 Key Features Features Details Application Processor Octa core ARM Cortex A53 64 bit CPU 2 0 GHz high performance One quad core with 1 MB L2 cache One quad core with 512 KB L2 cache Modem system Hexagon DSP V56 core up to 850 MHz 768 KB L2 caches GPU AdrenoTM 506 with 64 bit addressing designed for 650 MHz Memory 16 GB eMMC 2 GB LPDDR3 default 32 GB eMMC ...

Page 19: ...265 Mbps DL Max 30 Mbps UL Cat 4 FDD Max 150 Mbps DL Max 50 Mbps UL Cat 4 TDD Max 130 Mbps DL Max 30 Mbps UL UMTS Features Support 3GPP Rel 9 DC HSDPA DC HSUPA HSPA HSDPA HSUPA WCDMA Support QPSK 16QAM and 64QAM modulation DC HSDPA Max 42 Mbps DL DC HSUPA Max 11 2 Mbps UL WCDMA Max 384 kbps DL Max 384 kbps UL GSM Features R99 CSD 9 6 kbps 14 4 kbps GPRS Support GPRS multi slot class 33 33 by defau...

Page 20: ... WB GSM EFR GSM FR GSM HR USB Interface Support USB 3 0 or 2 0 with transmission rates up to 5 Gbps on USB 3 0 and 480 Mbps on USB 2 0 Support USB OTG Used for AT command communication data transmission software debugging and firmware upgrade UART Interfaces Three UART Interfaces UART5 UART4 and UART2 UART5 4 wire UART interface with hardware flow control RTS CTS baud rate up to 4 Mbps UART4 2 wir...

Page 21: ...face RoHS All hardware components are fully compliant with EU RoHS directive 1 Within the operating temperature range the module is 3GPP compliant 2 3 Functional Diagram The following figure shows a block diagram of the series and illustrates the major functional parts Power management Radio frequency Baseband LPDDR3 eMMC flash Peripheral interfaces VRTC interface USB interface UART interfaces U S...

Page 22: ...NA SAW SAW Switch SAW ANT_DRX ANT_ MAIN 19 2M XO PMU HK ADC MPPs PWM Headset VRTC APT VDD_RF PWRKEY C1 SD_LDO11 USIM1_VDD USIM2_VDD LDO6_1P8 LDO5_1P8 SD_LDO12 LDO22_2P8 LDO10_2P8 LDO17_2P85 LDO23_1P2 LDO2_1P1 VBAT VPH_PWR ANT_FM VOL_UP VOL_DOWN I2S Figure 1 Functional Diagram 2 4 Evaluation Board To help you develop applications with the module conveniently Quectel supplies an evaluation board a U...

Page 23: ...tion The following chapters describe in detail the pins interfaces listed below Power supply VRTC interface USB interface UART interfaces U SIM interfaces SD card interface GPIO interfaces I2C interfaces SPI interfaces ADC interface LCM interfaces TP interfaces Camera interfaces Sensor interfaces Audio interfaces USB_BOOT interface ...

Page 24: ...D 21 RESER VED 22 RESER VED 20 23 RESER VED 24 RESER VED 25 RESER VED 26 RESER VED 27 RESER VED 28 RESER VED 29 RESER VED 30 USB_ID 31 GN D 32 USB_DP 33 USB_DM 34 GN D 35 GN D 36 VBAT 37 VBAT 38 VBAT 114 LCD1_TE 113 LCD1_RST 112 GN D 111 DSI1_LN3_N 110 DSI1_LN3_P 109 DSI1_LN2_N 108 DSI1_LN2_P 107 DSI1_LN1_N 106 DSI1_LN1_P 105 DSI1_LN0_N 104 DSI1_LN0_P 103 DSI1_CLK_N 102 DSI1_CLK_P 101 GN D 100 SCA...

Page 25: ... input DO Digital output DIO Digital input output OD Open drain PI Power input PO Power output Power Supply Pin Name Pin No I O Description DC Characteristics Comment VBAT 36 37 38 PI PO Power supply for the module Vmax 4 4 V Vmin 3 55 V Vnom 3 8 V It must be provided with a sufficient current of at least 3 0 A It is suggested to use a TVS to increase the voltage surge withstand capability VDD_RF ...

Page 26: ...en LDO6_1P8 10 PO 1 8 V output power for I O VDD of cameras LCDs and sensors Vnom 1 8 V IOmax 300 mA Add a 1 0 2 2 μF bypass capacitor if the pin is used If unused keep this pin open LDO17_ 2P85 12 PO 2 85 V output power for cameras and LCDs Vnom 2 85 V IOmax 300 mA Add a 1 0 4 7 μF bypass capacitor if this pin is used If unused keep this pin open LDO23_1P2 15 PO 1 2 V output power for DVDD of the...

Page 27: ...e input for channel 1 MIC_GND 168 Microphone reference ground If this pin is unused connect it to the ground MIC2_P 46 AI Microphone input for headset MIC3_P 169 AI Microphone input for channel 2 EAR_P 53 AO Earpiece output EAR_N 52 AO Earpiece output SPK_P 55 AO Speaker output SPK_N 54 AO Speaker output HPH_R 51 AO Headphone right channel output HPH_REF 50 AI Headphone reference ground It should ...

Page 28: ...of this pin is not used it can be configured into a general purpose GPIO USB_SS_ RX_P 171 AI USB 3 0 super speed receive 90 Ω differential impedance USB 3 0 standard compliant USB_SS_ RX_M 172 AI USB 3 0 super speed receive USB_SS_ TX_P 174 AO USB 3 0 super speed transmit USB_SS_ TX_M 175 AO USB 3 0 super speed transmit USBC_CC2 223 AIO USB Type C control configuration channel 2 USBC_CC1 224 AIO U...

Page 29: ...quire to be pulled up to USIM1_VDD with a 10 kΩ resistor USIM1_VDD 141 PO U SIM1 card power supply 1 8 V U SIM Vmax 1 90 V Vmin 1 70 V 2 95 V U SIM Vmax 3 04 V Vmin 2 7 V Either 1 8 V or 2 95 V U SIM card is supported USIM2_DET 256 DI U SIM2 card hot plug detect VILmax 0 63 V VIHmin 1 17 V Active low Require to be externally pulled up to 1 8 V If unused keep this pin open Disabled by default and c...

Page 30: ...main If unused keep these pins open UART2_RXD 6 DI UART2 receive VILmax 0 63 V VIHmin 1 17 V UART4_TXD 7 DO UART4 transmit VOLmax 0 45 V VOHmin 1 35 V UART4_RXD 8 DI UART4 receive VILmax 0 63 V VIHmin 1 17 V UART5_RXD 198 DI UART5 receive VILmax 0 63 V VIHmin 1 17 V UART5_TXD 199 DO UART5 transmit VOLmax 0 45 V VOHmin 1 35 V UART5_RTS 245 DO UART5 request to send VOLmax 0 45 V VOHmin 1 35 V UART5_...

Page 31: ...PO SD card power supply Vnom 2 95 V IOmax 800 mA SD_LDO12 179 PO 1 8 2 95 V output power for SD card pull up circuits Vnom 1 8 2 95 V IOmax 50 mA TP Touch Panel Interfaces Pin Name Pin No I O Description DC Characteristics Comment TP0_RST 138 DO TP0 reset VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain Active low TP0_INT 139 DI TP0 interrupt VILmax 0 63 V VIHmin 1 17 V 1 8 V power domain TP0_I2C_SC...

Page 32: ...6 DI LCD0 tearing effect VILmax 0 63 V VIHmin 1 17 V 1 8 V power domain LCD1_RST 113 DO LCD1 reset VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain Active low LCD1_TE 114 DI LCD1 tearing effect VILmax 0 63 V VIHmin 1 17 V 1 8 V power domain DSI0_CLK_N 116 AO LCD0 MIPI clock DSI0_CLK_P 115 AO LCD0 MIPI clock DSI0_LN0_N 118 AO LCD0 MIPI lane 0 data DSI0_LN0_P 117 AO LCD0 MIPI lane 0 data DSI0_LN1_N 12...

Page 33: ...data Camera Interfaces Pin Name Pin No I O Description DC Characteristics Comment CSI0_CLK_N 89 AI MIPI clock of rear camera CSI0_CLK_P 88 AI MIPI clock of rear camera CSI0_LN0_N 91 AI MIPI lane 0 data of rear camera CSI0_LN0_P 90 AI MIPI lane 0 data of rear camera CSI0_LN1_N 93 AI MIPI lane 1 data of rear camera CSI0_LN1_P 92 AI MIPI lane 1 data of rear camera CSI0_LN2_N 95 AI MIPI lane 2 data of...

Page 34: ...I MIPI lane 3 data of depth camera CSI2_CLK_N 78 AI MIPI clock of front camera CSI2_CLK_P 77 AI MIPI clock of front camera CSI2_LN0_N 80 AI MIPI lane 0 data of front camera CSI2_LN0_P 79 AI MIPI lane 0 data of front camera CSI2_LN1_N 82 AI MIPI lane 1 data of front camera CSI2_LN1_P 81 AI MIPI lane 1 data of front camera CSI2_LN2_N 84 AI MIPI lane 2 data of front camera CSI2_LN2_P 83 AI MIPI lane ...

Page 35: ...Lmax 0 45 V VOHmin 1 35 V 1 8 V power domain DCAM_RST 180 DO Reset of depth camera VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain DCAM_PWDN 181 DO Power down of depth camera VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain DCAM_I2C_ SDA 197 OD I2C data of depth camera 1 8 V power domain DCAM_I2C_ SCL 196 OD I2C clock of depth camera 1 8 V power domain Keypad Interfaces Pin Name Pin No I O Descriptio...

Page 36: ...WIFI BT 129 AIO Wi Fi BT antenna interface FM_ANT 244 AI FM antenna interface GPIO Interfaces Pin Name Pin No I O Description DC Characteristics Comment GPIO_0 248 DIO General purpose input output VILmax 0 63 V VIHmin 1 17 V VOLmax 0 45 V VOHmin 1 4 V GPIO_2 201 DIO General purpose input output GPIO_3 200 DIO General purpose input output GPIO_33 238 DIO General purpose input output GPIO_36 237 DIO...

Page 37: ...acteristics Comment SPI_CS 58 DO SPI chip select SPI_CLK 59 DO SPI clock SPI_MOSI 60 DO SPI master out slave in SPI_MISO 61 DI SPI master in salve out FP_SPI_CS 203 DO FP SPI chip select FP_SPI_CLK 250 DO FP SPI clock FP_SPI_MOSI 249 DO FP SPI master out slave in FP_SPI_MISO 251 DI FP SPI master in salve out USB_BOOT Interface Pin Name Pin No I O Description DC Characteristics Comment USB_BOOT 57 ...

Page 38: ...y influences the module s performance and stability Under extreme conditions the module may have a transient peak current up to 3 A If the power supply capacity is not sufficient there will be the risk that the voltage drops below 3 1 V and as a result the module powers off automatically Therefore it is necessary to ensure that the input voltage never drops below 3 1 V GNSS_LNA_ EN 202 DO GNSS LNA...

Page 39: ...e it is suggested to place a 2000 W TVS as close to the VBAT pins as possible to increase voltage surge withstand capability The following figure shows the structure of the power supply Module VPH_PWR VBAT VBAT C1 100 μF C6 100 nF C7 C8 C2 100 nF C3 33 pF C4 D1 VDD_RF VPH_PWR C10 C11 C12 33 pF 33 pF 10 pF 10 pF 10 pF 100 nF Figure 4 Star Structure of Power Supply 3 4 3 Reference Design for Power S...

Page 40: ...00K 47K R3 470 μF 470R 51K R4 R1 1 1 Figure 5 Reference Design for Power Supply If the module happens to get into an abnormal state it is recommended to switch off and on its power supply to restart it 3 5 Turn On and Turn Off Timing 3 5 1 Turn On Module The PWRKEY pin is pulled up to 1 8 V internally Driving it low for at least 1 6 s turns on the module It is recommended to control the pin with a...

Page 41: ... TVS 1K Figure 7 Turn On Module Using Button The timing of turning on the module is illustrated in the following figure VBAT Typ 3 8 V PWRKEY 1 6 s Others LDO5_1P8 38 s LDO6_1P8 61 2 ms Software controlled LDO17_2P85 Active LDO10_2P8 Note2 Software controlled Figure 8 Power up Timing 1 When the module powers on for the first time the power up timing might be different from what is shown in the fig...

Page 42: ...EY Others 8 s Power down Figure 9 Power off Timing 3 6 VRTC Interface The RTC Real Time Clock can be powered by an external power source through VRTC when the module is powered down and there is no power supplied to the VBAT The external power source can be a rechargeable battery such as coil cells according to application demands The following figure shows a reference design for powering RTC with...

Page 43: ...ated voltages for peripheral circuits During application it is recommended to use parallel capacitors 33 pF and 10 pF on the circuits to suppress high frequency noise Table 8 Power Description Pin Name Default Voltage V Drive Current mA Comment LDO5_1P8 1 8 20 So long as the module is powered on the pin retains its power LDO6_1P8 1 8 300 LDO10_2P8 2 8 150 LDO17_2P85 2 85 300 LDO2_1P1 1 1 1200 LDO2...

Page 44: ...ption Comment USB_VBUS 41 42 AI USB connection detect Vmax 10 0 V Vmin 4 0 V Vnom 5 0 V USB_DM 33 AIO USB differential data 90 Ω differential impedance USB 2 0 standard compliant USB_DP 32 AIO USB differential data USB_ID 1 30 DO USB ID detect High level by default GPIO_1 247 DI USB ID interrupt detection Pulled up internally If the default function is not used it can be configured into a general ...

Page 45: ...PIO_1 directly to the USB_ID of external micro USB interface for USB ID detection If the external micro USB interface serves as a host the module s GPIO_1 will be pulled down to force the module into Host mode The following figure is a reference design for the USB 2 0 interface USB_DP USB_DM USB_VBUS 1 2 3 4 5 USB_DP USB_DM VBUS USB_ID GND GND GND GND GND 6 7 8 9 100 nF Module C1 D1 D2 D3 ESD ESD ...

Page 46: ... USB performance please follow these principles in your design Route the USB signal traces as differential pairs with total grounding and keep the impedance of USB differential traces at 90 Ω Pay attention to the influence of junction capacitance of ESD protection devices upon USB data lines Typically the capacitance should be less than 2 pF for USB 2 0 and less than 0 5 pF for USB 3 0 Avoid routi...

Page 47: ...nterface with 1 8 V power domain A level translator chip should be used if your Pin No Signal Length mm Length Difference mm 33 USB_DM 39 52 0 45 32 USB_DP 39 07 171 USB_SS_RX_P 28 55 0 32 172 USB_SS_RX_M 28 23 174 USB_SS_TX_P 19 58 0 23 175 USB_SS_TX_M 19 35 Pin Name Pin No I O Description Comment UART2_TXD 5 DO UART2 transmit 1 8 V power domain Keep the unused of these pins open UART2_RXD 6 DI U...

Page 48: ...l Translator Chip for UART5 The following figure is an example connection between the module and PC A voltage level translator and an RS 232 transceiver are recommended to be added between the module and PC as shown in the figure below TXS0104EPWR RXD _3 3V CTS _3 3V VCCA Module GND GND 1 8V VCCB 3 3V DIN1 ROUT3 ROUT 2 ROUT1 DIN4 DIN3 DIN2 DIN 5 FORCEON 3 3V DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 RIN3 RIN2...

Page 49: ... plug detect Active low Require to be externally pulled up to 1 8 V If unused keep this pin open Disabled by default and can be enabled through software configuration USIM1_RST 144 DO U SIM1 card reset USIM1_CLK 143 DO U SIM1 card clock USIM1_DATA 142 DIO U SIM1 card data Require to be pulled up to USIM1_VDD with a 10 kΩ resistor USIM1_VDD 141 PO U SIM1 card power supply Either 1 8 V or 2 95 V U S...

Page 50: ...R4 C2 C3 C4 USIM_DET U SIM Card Connector Figure 16 Reference Design for U SIM Interface with a 6 pin U SIM Card Connector To ensure good performance and avoid damage of U SIM cards please follow these principles in your design Place the U SIM card connector as close to the module as possible Keep the U SIM trace length as less than 200 mm as possible Keep U SIM card signal traces away from RF and...

Page 51: ...s with SD 3 0 specifications The pin definition of the SD card interface is shown below Table 13 Pin Definition of SD Card Interface A reference design for SD card interface is shown as below Pin Name Pin No I O Description Comment SD_LDO11 63 PO SD card power supply Vnom 2 95 V IOmax 800 mA SD_LDO12 179 PO 1 8 2 95 V output power for SD card pull up circuits 1 8 2 95 V output SD_CLK 70 DO SD card...

Page 52: ...above To ensure the stability of supply power a 4 7 μF and a 33 pF capacitor should be added in parallel near the SD card connector SD_CMD SD_CLK SD_DATA0 SD_DATA1 SD_DATA2 and SD_DATA3 traces are all high speed signal traces In PCB design control the characteristic impedance of these traces at 50 Ω 10 and avoid crossing them with other traces It is recommended to route the traces on the inner lay...

Page 53: ...ose input output GPIO_3 200 General purpose input output GPIO_33 238 General purpose input output GPIO_36 237 General purpose input output Wakeup GPIO_42 252 General purpose input output Wakeup GPIO_43 253 General purpose input output Wakeup GPIO_44 254 General purpose input output Wakeup GPIO_45 255 General purpose input output Wakeup GPIO_66 234 General purpose input output GPIO_89 232 General p...

Page 54: ...I2C Interfaces 3 14 SPI Interfaces The module provides two SPI interfaces which only support Master mode The two interfaces are typically applied for fingerprint identification Pin Name Pin No I O Description Comment TP0_I2C_SCL 140 OD TP0 I2C clock Used for TP0 TP0_I2C_SDA 206 OD TP0 I2C data TP1_I2C_SCL 205 OD TP1 I2C clock Used for TP1 TP1_I2C_SDA 204 OD TP1 I2C data CAM_I2C_SCL 75 OD I2C clock...

Page 55: ... dual LCDs and features WUXGA display with a resolution up to 1200 RGB 1920 These interfaces support high speed differential data transmission along up to 8 lanes Pin Name Pin No I O Description Comment SPI_CS 58 DO SPI chip select SPI_CLK 59 DO SPI clock SPI_MOSI 60 DO SPI master out slave in SPI_MISO 61 DI SPI master in salve out FP_SPI_CS 203 DO FP SPI chip select FP_SPI_CLK 250 DO FP SPI clock...

Page 56: ...e configured into a general purpose GPIO LCD0_RST 127 DO LCD0 reset Active low LCD0_TE 126 DI LCD0 tearing effect LCD1_RST 113 DO LCD1 reset Active low LCD1_TE 114 DI LCD1 tearing effect DSI0_CLK_N 116 AO LCD0 MIPI clock DSI0_CLK_P 115 AO LCD0 MIPI clock DSI0_LN0_N 118 AO LCD0 MIPI lane 0 data DSI0_LN0_P 117 AO LCD0 MIPI lane 0 data DSI0_LN1_N 120 AO LCD0 MIPI lane 1 data DSI0_LN1_P 119 AO LCD0 MI...

Page 57: ...4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 MIPI_TDP0 MIPI_TDN0 GND MIPI_TCP MIPI_TCN 29 28 30 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 DSI0_LN1_N DSI0_LN1_P DSI0_LN0_N DSI0_LN0_P 1 2 3 4 5 6 11 1 2 1 2 1 2 1 2 100 nF 4 7μF 1 μF Module LCM0 FL1 FL2 FL3 FL4 FL5 EMI filter C3 C2 C1 NC GND GND GND GND PMI_MPP1 31 32 33 34 Figure 18 Reference Design for LCM0 Interface DSI1_LN0_P 104 AO LCD1 ...

Page 58: ...1 2 3 4 5 6 11 1 2 1 2 1 2 1 2 100 nF 4 7 μF 1 μF Module LCM1 FL1 FL2 FL3 FL4 FL5 EMI filter C3 C2 C1 NC GND GND GND GND PMU_MPP2 31 32 33 34 LCM1_LED Figure 19 Reference Design for LCM1 Interface For high speed MIPI_CSI signals common mode filters should be added in series near the LCM connector to improve protection against electromagnetic radiation interference When compatible design with other...

Page 59: ...the touch panel interfaces is illustrated below Table 20 Pin Definition of Touch Panel Interfaces Pin Name Pin No I O Description Comment LDO10_2P8 11 PO 2 8 V output power for VDD of Sensor and TP Vnom 2 8 V IOmax 150 mA LDO6_1P8 10 PO 1 8 V output power for VDD of Sensor Camera LCD and I2C s pull up circuits Vnom 1 8 V IOmax 300 mA TP0_INT 139 DI TP0 Interrupt 1 8 V power domain TP0_RST 138 DO T...

Page 60: ... When dual TP or other applications need to be supported it is recommended to use an external LDO instead 3 18 Camera Interfaces Based on standard MIPI_CSI input interface The module supports 3 cameras 4 lane 4 lane 4 lane or 4 cameras 4 lane 4 lane 2 lane 1 lane The video and photo quality is determined by various factors such as the quality of camera sensor and camera lens Table 21 Pin Definitio...

Page 61: ... of rear camera CSI0_LN1_N 93 AI MIPI lane 1 data of rear camera CSI0_LN1_P 92 AI MIPI lane 1 data of rear camera CSI0_LN2_N 95 AI MIPI lane 2 data of rear camera CSI0_LN2_P 94 AI MIPI lane 2 data of rear camera CSI0_LN3_N 97 AI MIPI lane 3 data of rear camera CSI0_LN3_P 96 AI MIPI lane 3 data of rear camera CSI1_CLK_N 184 AI MIPI clock signal of depth camera CSI1_CLK_P 183 AI MIPI clock signal of...

Page 62: ...clock of rear camera 1 8 V power domain SCAM_MCLK 100 DO Master clock of front camera 1 8 V power domain MCAM_RST 74 DO Reset of rear camera 1 8 V power domain MCAM_PWDN 73 DO Power down of rear camera 1 8 V power domain SCAM_RST 72 DO Reset of front camera 1 8 V power domain SCAM_PWDN 71 DO Power down of front camera 1 8 V power domain CAM_I2C_SCL 75 OD I2C clock of front and rear cameras 1 8 V p...

Page 63: ...ont camera connector 4 7μF 1μF 1μF MCAM_RST EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI LDO17_2P85 AVDD AF_VDD DVDD DOVDD 1 μ F CSI0_LN0_P CSI0_LN0_N CSI0_LN1_P CSI0_LN1_N CSI0_LN2_P CSI0_LN2_N CSI0_LN3_P CSI0_LN3_N CSI2_LN0_P CSI2_LN0_N CSI2_LN1_P CSI2_LN1_N CSI2_LN2_P CSI2_LN2_N CSI2_LN3_P CSI2_LN3_N LDO23_1P2 DVDD 1 μ F 4 7 μF 4 7 μ F AVDD DOVDD Figure 22 Reference Design for Dual Camera Applicatio...

Page 64: ... 7 μF 4 7 μF 1 μF 1 μF 4 7 μ F MCAM_RST DCAM_PWDN DCAM_MCLK DCAM_I2C_SDA _ DCAM_I2C_SCL DCAM_RST Depth camera connector LDO17_2P85 AVDD AF_VDD DVDD DOVDD EMI EMI EMI EMI EMI EMI EMI EMI LDO2_1P1 1 μF LDO23_1P2 2 2K 2 2K DVDD EMI EMI 4 7 1μF μF AVDD DOVDD Figure 23 Reference Design for Triple Camera Application 3 18 1 Design Considerations Pay attention to the pin definitions of LCM and camera conn...

Page 65: ...pF Route MIPI traces according to the following rules a The total trace length should not exceed 305 mm b Keep the differential impedance at 100 Ω 10 c Control the intra lane length difference within 0 67 mm d Control the inter lane length difference within 1 3 mm Table 22 MIPI Trace Length Inside the Module Pin Name Pin No Length mm Length Difference mm DSI0_CLK_N 116 20 82 0 45 DSI0_CLK_P 115 20...

Page 66: ...1 17 47 0 07 CSI0_LN0_P 90 17 4 CSI0_LN1_N 93 12 13 0 05 CSI0_LN1_P 92 12 08 CSI0_LN2_N 95 9 56 0 14 CSI0_LN2_P 94 9 7 CSI0_LN3_N 97 8 73 0 13 CSI0_LN3_P 96 8 86 CSI1_CLK_N 184 20 32 0 23 CSI1_CLK_P 183 20 09 CSI1_LN0_N 186 12 09 0 57 CSI1_LN0_P 185 12 66 CSI1_LN1_N 188 11 33 0 37 CSI1_LN1_P 187 11 70 CSI1_LN2_N 190 5 86 0 19 CSI1_LN2_P 189 6 05 CSI1_LN3_N 192 10 49 0 43 CSI1_LN3_P 191 10 06 CSI2_...

Page 67: ...in Name Pin No I O Description Comment SENSOR_I2C_SCL 131 OD I2C clock for external sensor Dedicated for external sensors Cannot be used for other devices such as touch panel NFC and keypad SENSOR_I2C_SDA 132 OD I2C data for external sensor 3 20 Audio Interfaces The module provides three analog input channels and three analog output channels The following table shows the pin definition CSI2_LN0_N ...

Page 68: ...REF 50 AI Headphone reference ground It should be connected to the main GND HPH_L 49 AO Headphone left channel output HS_DET 48 AI Headset hot plug detect High level by default The module offers three audio input channels including one differential input pair and two single ended channels The three sets of MICs are integrated with internal bias voltage The output voltage range of MIC_BIAS can be s...

Page 69: ...ign for Microphone Interfaces MIC1_P ECM MIC R2 R1 Module D1 MIC1_N 33 pF C1 0R 0R R3 0R Figure 24 Reference Design for Analog ECM type Microphone MIC3_P 33 pF MEMS MIC R2 R1 C2 Module MIC_GND 0R C1 MIC_BIAS 1 2 3 4 F1 D1 OUT GND GND VDD 100 pF C4 0R 33 pF Figure 25 Reference Design for MEMS type Microphone ...

Page 70: ...pF 33 pF 33 pF C2 C3 C1 R1 Module D1 D2 0R 0R Figure 26 Reference Design for Earpiece Interface 3 20 3 Reference Design for Headphone Interface 20K ESD MIC_GND MIC2_P HPH_L HS_DET HPH_R HPH_REF 33 pF Module R1 0R 3 6 4 5 2 1 33 pF 33 pF C3 C4 C5 F3 F2 F1 D1 D2 D3 D4 F4 R2 R3 0R Figure 27 Reference Design for Headphone Interface with Normally Open Jack ...

Page 71: ...able capacitor for filtering out high frequency noises after consulting your capacitor supplier The severity degree of the RF interference in the voice channel during GSM transmitting largely depends on the application design In some cases EGSM900 TDD noise is more severe while in other cases DCS1800 TDD noise is more obvious Therefore a suitable capacitor should be selected based on test results ...

Page 72: ...Smart Module Series SC606T Series Hardware Design SC606T_Series_Hardware_Design 71 116 the reference design shown below LDO5_1P8 S1 Module USB_BOOT R1 10K Figure 29 Reference Design for USB_BOOT ...

Page 73: ... GHz dual band WLAN wireless communications based on IEEE 802 11a b g n ac standard protocols The maximum data rate is 433 Mbps The features available are as follows Support Wake on WLAN WoWLAN Support ad hoc mode Support WAPI SMS4 hardware encryption Support AP mode Support Wi Fi Direct Support MCS 0 7 for HT20 and HT40 Support MCS 0 8 for VHT20 Support MCS 0 9 for VHT40 and VHT80 4 1 1 Wi Fi Per...

Page 74: ... dB 802 11a 54Mbps 13 dBm 2 5 dB 802 11n HT20 MCS0 15 dBm 2 5 dB 802 11n HT20 MCS7 13 dBm 2 5 dB 802 11n HT40 MCS0 15 dBm 2 5 dB 802 11n HT40 MCS7 13 dBm 2 5 dB 802 11ac VHT20 MCS0 15 dBm 2 5 dB 802 11ac VHT20 MCS8 13 dBm 2 5 dB 802 11ac VHT40 MCS0 14 dBm 2 5 dB 802 11ac VHT40 MCS9 13 dBm 2 5 dB 802 11ac VHT80 MCS0 13 dBm 2 5 dB 802 11ac VHT80 MCS9 12 dBm 2 5 dB Standard Rate Sensitivity 2 4 GHz 8...

Page 75: ...GFSK 8 DPSK π 4 DQPSK modulation modes Support up to 7 wireless connections Support up to 3 5 piconets at the same time Support one SCO or eSCO Extended Synchronous Connection Oriented connection The BR EDR channel bandwidth is 1 MHz and can accommodate 79 channels The BLE channel bandwidth is 2 MHz and can accommodate 40 channels 802 11n HT20 MCS7 69 dBm 802 11n HT40 MCS0 85 dBm 802 11n HT40 MCS7...

Page 76: ...ifications Core_v4 2 December 12 2014 4 2 1 BT Performance The following table lists the BT transmitting and receiving performance of the module Table 28 BT Transmitting and Receiving Performance Version Data rate Maximum Application Throughput 1 2 1 Mbit s 80 kbit s 2 0 EDR 3 Mbit s 80 kbit s 3 0 HS 24 Mbit s Refer to 3 0 HS 4 0 24 Mbit s Refer to 4 0 LE 4 2 60 Mbit s Refer to 4 2 LE Transmitter ...

Page 77: ...uction mode Table 29 GNSS Performance 5 2 GNSS Design Guidelines Bad design of antenna signal traces layout may cause reduced GNSS receiving sensitivity longer GNSS positioning time and reduced positioning accuracy To avoid these follow the design rules listed below Maximize the distance between the GNSS RF part and the GPRS RF part including trace routing and antenna traces layout to avoid mutual...

Page 78: ...romagnetic environment or high ESD protection requirements it is recommended to add ESD protection diodes for the antenna interface Only diodes with ultra low junction capacitance such as 0 5 pF can be selected Otherwise there will be effects on the impedance characteristic of the RF circuit loop or attenuation of the bypass RF signal may be caused Control the impedance of both the antenna feeder ...

Page 79: ...rsity antenna interfaces is shown below Table 30 Pin Definition of Main and Rx diversity Antenna Interfaces The operating frequencies of the series are listed in the following tables Table 31 SC606T JP Operating Frequencies Pin Name Pin No I O Description Comment ANT_MAIN 19 AIO Main antenna interface 50 Ω impedance ANT_DRX 149 AI Diversity and MIMO antenna interface 50 Ω impedance 3GPP Band Recei...

Page 80: ...6 758 788 703 733 MHz LTE FDD B28A 758 788 703 733 MHz LTE FDD B28B 773 803 718 748 MHz LTE TDD B41 1 2496 2690 2496 2690 MHz 3GPP Band Receive Transmit Unit GSM850 869 894 824 849 MHz EGSM900 925 960 880 915 MHz DCS1800 1805 1880 1710 1785 MHz PCS1900 1930 1990 1850 1910 MHz WCDMA B1 2110 2170 1920 1980 MHz WCDMA B2 1930 1990 1850 1910 MHz WCDMA B4 2110 2155 1710 1755 MHz WCDMA B5 869 894 824 849...

Page 81: ... 718 748 MHz LTE TDD B38 2570 2620 2570 2620 MHz LTE TDD B40 2300 2400 2300 2400 MHz LTE TDD B41 1 2496 2690 2496 2690 MHz 3GPP Band Receive Transmit Unit WCDMA B2 1930 1990 1850 1910 MHz WCDMA B4 2110 2155 1710 1755 MHz WCDMA B5 869 894 824 849 MHz LTE FDD B2 1930 1990 185 1910 MHz LTE FDD B4 2110 2155 1710 1755 MHz LTE FDD B5 869 894 824 849 MHz LTE FDD B7 2620 2690 2500 2570 MHz LTE FDD B12 729...

Page 82: ...s below A π type matching circuit should be reserved for both ANT_MAIN and ANT_DRX for better RF performance and the π type matching components R1 C1 C2 R2 C3 C4 should be placed as close to the antennas as possible The capacitors are not mounted by default and the resistors are 0 Ω ANT_MAIN R1 0R C1 Module Main antenna NM C2 NM R2 0R C3 Diversity antenna NM C4 NM ANT_DRX Figure 30 Reference Circu...

Page 83: ... dielectric constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or coplanar waveguide with different PCB structures Figure 31 Microstrip Design on a 2 layer PCB Figure 32 Coplanar Wavegu...

Page 84: ...traces should be changed to curve ones There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias around RF traces and the reference ground could help to improve RF performance The distance between the ground vias and RF traces should be no less than two times as wide as RF signal tr...

Page 85: ...faces for better RF performance The capacitors are not mounted by default and resistors are 0 Ω ANT_WIFI BT R1 0R C1 Module NM C2 NM Figure 35 Reference Circuit Design for Wi Fi BT Antenna Interface ANT_FM R1 0R C1 Module NM C2 NM Figure 36 Reference Circuit Design for FM Antenna Interface 6 3 GNSS Antenna Interface The pin definition of GNSS antenna interface and operating frequencies are shown b...

Page 86: ...NM C1 C2 R1 C4 NM 0R Figure 37 Reference Design for GNSS Passive Antenna When the passive antenna is placed far away from the module and the trace is long it is recommended to add an external LNA circuit for better GNSS receiving performance and the LNA should be placed close to the antenna Pin Name Pin No I O Description Comment ANT_GNSS 134 AI GNSS antenna Interface 50 Ω impedance GNSS_LNA_EN 20...

Page 87: ...ltage for the active antenna A reference design of GNSS active antenna is shown below 3V3 Module ANT_GNSS 56 nH 10R 1 μF 100 pF NM NM C4 C1 R1 L1 R2 0R C5 C3 C2 100 pF R4 R3 R5 Active Antenna 0R Figure 38 Reference Design for GNSS Active Antenna It is strongly recommended to reserve the π type attenuation network 6 4 Antenna Installation 6 4 1 Antenna Requirements The following table shows the req...

Page 88: ...le Insertion Loss 1 dB GSM850 EGSM900 WCDMA B5 B6 B8 B19 LTE B5 B8 B12 B13 B14 B17 B18 B19 B20 B26 B28A B28B B71 Cable Insertion Loss 1 5 dB DCS1800 PCS1900 WCDMA B1 B2 B4 LTE B1 B2 B3 B4 B11 B21 B25 B34 B39 B66 Cable Insertion Loss 2 dB LTE FDD B7 LTE TDD B38 B40 B41 Wi Fi BT VSWR 2 Gain dBi 1 Max Input Power W 50 Input Impedance Ω 50 Polarization Type Vertical Cable Insertion Loss 1 dB GNSS 1 Fr...

Page 89: ...gn 88 116 Figure 39 Dimensions of the U FL R SMT Connector Unit mm The U FL LP serial connectors listed in the following figure can be used to match the U FL R SMT Figure 40 Mechanicals of U FL LP Connectors The following figure describes the form factor of the mated connectors ...

Page 90: ...Smart Module Series SC606T Series Hardware Design SC606T_Series_Hardware_Design 89 116 Figure 41 Form Factor of Mated Connectors Unit mm For more details please visit http www hirose com ...

Page 91: ... listed in the following table Table 39 Absolute Maximum Ratings 7 2 Operating Power Table 40 Operating Power Parameter Min Max Unit VBAT 0 5 6 V USB_VBUS 0 3 10 V Current on VBAT 0 3 A Voltage on Digital Pins 0 3 2 16 V Parameter Description Conditions Min Typ Max Unit VBAT Peak supply voltage for VBAT The actual input voltage must fall between the minimum and maximum values 3 55 3 8 4 4 V Voltag...

Page 92: ...umptions of the module in different conditions are listed in the following tables Table 42 SC606T JP Current Consumption IVBAT Peak supply current during a transmission slot Maximum power control level at EGSM900 1 8 3 0 A USB_VBUS 4 0 5 0 6 0 V VRTC Supply voltage of a backup battery 2 0 3 0 3 25 V Parameter Min Typ Max Unit Operating temperature range 1 35 25 75 C Storage temperature range 40 90...

Page 93: ...3 mA WCDMA voice call B1 max power 597 mA B6 max power 620 mA B8 max power 584 mA B19 max power 610 mA WCDMA data transfer B1 HSDPA max power 550 mA B6 HSDPA max power 580 mA B8 HSDPA max power 550 mA B19 HSDPA max power 580 mA B1 HSUPA max power 562 mA B6 HSUPA max power 595 mA B8 HSUPA max power 556 mA B19 HSUPA max power 600 mA LTE data transfer LTE FDD B1 max power 570 mA LTE FDD B3 max power ...

Page 94: ... Power down 80 μA GSM supply current Sleep USB disconnected DRX 2 4 5 mA Sleep USB disconnected DRX 5 3 5 mA Sleep USB disconnected DRX 9 3 mA WCDMA supply current Sleep USB disconnected DRX 6 3 47 mA Sleep USB disconnected DRX 8 3 11 mA Sleep USB disconnected DRX 9 2 75 mA LTE FDD supply current Sleep USB disconnected DRX 6 3 85 mA Sleep USB disconnected DRX 8 2 96 mA LTE TDD supply current Sleep...

Page 95: ...0 PCL 15 125 mA WCDMA voice call B1 max power 620 mA B2 max power 550 mA B4 max power 580 mA B5 max power 590 mA B8 max power 560 mA GPRS data transfer GSM850 1UL 4DL PCL 5 240 mA GSM850 2UL 3DL PCL 5 370 mA GSM850 3UL 2DL PCL 5 440 mA GSM850 4UL 1DL PCL 5 500 mA EGSM900 1UL 4DL PCL 5 260 mA EGSM900 2UL 3DL PCL 5 380 mA EGSM900 3UL 2DL PCL 5 490 mA EGSM900 4UL 1DL PCL 5 520 mA DCS1800 1UL 4DL PCL ...

Page 96: ...L 2DL PCL 8 320 mA GSM850 4UL 1DL PCL 8 370 mA EGSM900 1UL 4DL PCL 8 170 mA EGSM900 2UL 3DL PCL 8 260 mA EGSM900 3UL 2DL PCL8 340 mA EGSM900 4UL 1DL PCL 8 380 mA DCS1800 1UL 4DL PCL 2 170 mA DCS1800 2UL 3DL PCL 2 260 mA DCS1800 3UL 2DL PCL 2 330 mA DCS1800 4UL 1DL PCL 2 400 mA PCS1900 1UL 4DL PCL 2 170 mA PCS1900 2UL 3DL PCL 2 260 mA PCS1900 3UL 2DL PCL 2 400 mA PCS1900 4UL 1DL PCL 2 410 mA WCDMA ...

Page 97: ...ax power 550 mA B5 HSUPA max power 520 mA B8 HSUPA max power 520 mA LTE data transfer LTE FDD B1 max power 550 mA LTE FDD B2 max power 530 mA LTE FDD B3 max power 650 mA LTE FDD B4 max power 530 mA LTE FDD B5 max power 560 mA LTE FDD B7 max power 680 mA LTE FDD B8 max power 550 mA LTE FDD B20 max power 530 mA LTE FDD B28A max power 580 mA LTE FDD B28B max power 570 mA LTE TDD B38 max power 600 mA ...

Page 98: ...DD B1 23 dBm 2 dB 39 dBm LTE FDD B3 23 dBm 2 dB 39 dBm LTE FDD B5 23 dBm 2 dB 39 dBm LTE FDD B8 23 dBm 2 dB 39 dBm LTE FDD B11 23 dBm 2 dB 39 dBm LTE FDD B18 23 dBm 2 dB 39 dBm LTE FDD B19 23 dBm 2 dB 39 dBm LTE FDD B21 23 dBm 2 dB 39 dBm LTE FDD B26 23 dBm 2 dB 39 dBm LTE FDD B28A 23 dBm 2 dB 39 dBm LTE FDD B28B 23 dBm 2 dB 39 dBm LTE TDD B41 23 dBm 2 dB 39 dBm Frequency Max Min GSM850 33 dBm 2 d...

Page 99: ...LTE FDD B2 23 dBm 2 dB 39 dBm LTE FDD B3 23 dBm 2 dB 39 dBm LTE FDD B4 23 dBm 2 dB 39 dBm LTE FDD B5 23 dBm 2 dB 39 dBm LTE FDD B7 23 dBm 2 dB 39 dBm LTE FDD B8 23 dBm 2 dB 39 dBm LTE FDD B20 23 dBm 2 dB 39 dBm LTE FDD B28A 23 dBm 2 dB 39 dBm LTE FDD B28B 23 dBm 2 dB 39 dBm LTE TDD B38 23 dBm 2 dB 39 dBm LTE TDD B40 23 dBm 2 dB 39 dBm LTE TDD B41 23 dBm 2 dB 39 dBm Frequency Max Min WCDMA B2 24 dB...

Page 100: ...ule Table 47 SC606T JP RF Receiving Sensitivity LTE FDD B4 23 dBm 2 dB 39 dBm LTE FDD B5 23 dBm 2 dB 39 dBm LTE FDD B7 23 dBm 2 dB 39 dBm LTE FDD B12 23 dBm 2 dB 39 dBm LTE FDD B13 23 dBm 2 dB 39 dBm LTE FDD B14 23 dBm 2 dB 39 dBm LTE FDD B17 23 dBm 2 dB 39 dBm LTE FDD B25 23 dBm 2 dB 39 dBm LTE FDD B26 23 dBm 2 dB 39 dBm LTE FDD B66 23 dBm 2 dB 39 dBm LTE FDD B71 23 dBm 2 dB 39 dBm LTE TDD B41 23...

Page 101: ...TE FDD B11 10 MHz 96 97 99 96 3 dBm LTE FDD B18 10 MHz 97 98 100 96 3 dBm LTE FDD B19 10 MHz 97 98 100 96 3 dBm LTE FDD B21 10 MHz 97 96 5 99 5 96 3 dBm LTE FDD B26 10 MHz 97 98 100 93 8 dBm LTE FDD B28A 10 MHz 95 97 98 5 94 8 dBm LTE FDD B28B 10 MHz 95 97 98 5 94 8 dBm LTE TDD B41 10 MHz 95 96 98 94 3 dBm Frequency Receive Sensitivity Typ 3GPP SIMO Primary Diversity SIMO GSM850 109 102 4 dBm EGSM...

Page 102: ... B7 10 MHz 96 96 99 94 3 dBm LTE FDD B8 10 MHz 97 5 97 5 100 5 93 3 dBm LTE FDD B20 10 MHz 96 5 97 5 100 93 3 dBm LTE FDD B28A 1 0MHz 97 96 5 99 5 94 8 dBm LTE FDD B28B 10 MHz 97 95 5 99 94 8 dBm LTE TDD B38 10 MHz 96 5 96 99 96 3 dBm LTE TDD B40 10 MHz 96 5 95 5 99 96 3 dBm LTE TDD B41 10 MHz 96 5 95 5 99 94 3 dBm Frequency Receive Sensitivity Typ 3GPP SIMO Primary Diversity SIMO WCDMA B2 109 109...

Page 103: ...ule The following table shows the electrostatic discharge characteristics of the module Table 50 ESD Characteristics Temperature 25 C Humidity 45 LTE FDD B7 10 MHz 96 96 98 94 3 dBm LTE FDD B12 10 MHz 96 97 5 98 5 93 3 dBm LTE FDD B13 10 MHz 95 5 97 5 98 93 3 dBm LTE FDD B14 10 MHz 97 97 99 93 3 dBm LTE FDD B17 10 MHz 96 97 98 93 3 dBm LTE FDD B25 10 MHz 97 97 99 92 8 dBm LTE FDD B26 10 MHz 97 5 9...

Page 104: ...l Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimension tolerances are 0 05 mm unless otherwise specified 8 1 Mechanical Dimensions of the Module S i de vi ew Top vi ew P i n1 Figure 42 Top and Side Dimensions Unit mm ...

Page 105: ... Module Series SC606T Series Hardware Design SC606T_Series_Hardware_Design 104 116 Figure 43 Bottom Dimensions Perspective View The package warpage level of the module conforms to JEITA ED 7306 standard NOTE ...

Page 106: ...ign 105 116 8 2 Recommended Footprint Figure 44 Recommended Footprint Perspective View 1 For easy maintenance of the module keep about 3 mm between the module and other components on the host PCB 2 All RESERVED pins should be kept open and MUST NOT be connected to ground NOTES ...

Page 107: ...ardware_Design 106 116 8 3 Top and Bottom Views of the Module Figure 45 Top and Bottom Views Images above are for illustration purpose only and may differ from the actual module For authentic appearance and label please refer to the module received from Quectel NOTE ...

Page 108: ...ed the module must be processed in reflow soldering or other high temperature operations within 168 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommended Stora...

Page 109: ...ce of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass To ensure the module soldering quality the thickness of stencil for the module is recommended to be 0 18 0 20 mm It is recommended to slightly reduce the amount of solder paste for LGA pads thus a...

Page 110: ...n the shielding can is still clearly identifiable and the QR code is still readable although white rust may be found 3 If a conformal coating is necessary for the module do NOT use any coating material that may chemically react with the PCB or shielding cover and prevent the coating material from flowing into the module 9 3 Packaging SC606T series module is packaged in tape and reel carriers Each ...

Page 111: ...ign 110 116 Figure 47 Tape Dimensions Figure 48 Reel Dimensions Table 52 Reel Packaging Model Name MOQ for MP Minimum Package 200 pcs Minimum Package 4 800 pcs SC606T series 200 Size 398 mm 383 mm 83 mm N W 1 92 kg G W 3 67 kg Size 420 mm 350 mm 405 mm N W 8 18 kg G W 15 18 kg ...

Page 112: ...rier Aggregation CS Coding Scheme CSD Circuit Switched Data CSI Channel State Information CTS Clear to Send DIP Dual In line Package SN Document Name Description 1 Quectel_Smart_EVB G2_User_Guide EVB User Guide for SC606T Series 2 Quectel_SC606T_Series_GPIO_Configuration GPIO Configuration of SC606T Series 3 Quectel_RF_Layout_Application_Note RF Layout Application Note 4 Quectel_Module_Secondary_S...

Page 113: ...onnection Oriented ESD Electrostatic Discharge ESR Equivalent Series Resistance FEM Front End Module FM Frequency Modulation FR Full Rate GLONASS Globalnaya Navigazionnaya Sputnikovaya Sistema the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GPS Global Positioning System GPU Graphics Processing Unit GSM Global System for Mobile Communications HR Half Rate HSDPA Hig...

Page 114: ...um Access Control MCS Modulation and Coding Scheme MEMS Micro Electro Mechanical System MIMO Multiple Input Multiple Output MIPI Mobile Industry Processor Interface MO Mobile Originated Origination MP Megapixel MT Mobile Terminal Termination OTG On The Go PCB Printed Circuit Board PDU Protocol Data Unit PHY Physical PMI Power Management Interface PMU Power Management Unit PSK Phase Shift Keying QA...

Page 115: ...rial Peripheral Interface STA Station TDD Time Division Distortion TE Terminal Equipment TP Touch Panel TX Transmitting Direction UART Universal Asynchronous Receiver Transmitter UL Uplink UMTS Universal Mobile Telecommunications System U SIM Universal Subscriber Identity Module VI Voltage Input VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value Vmax Maximum...

Page 116: ...116 VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network WLED White Light Emitting Diode WUXGA Widescreen Ultra Extended Graphics Array ...

Page 117: ...Coding Schemes Table 55 Description of Different Coding Schemes Scheme CS 1 CS 2 CS 3 CS 4 Code Rate 1 2 2 3 3 4 1 USF 3 3 3 3 Pre coded USF 3 6 6 12 Radio Block excl USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 Coded Bits 456 588 676 456 Punctured Bits 0 132 220 Data Rate Kb s 9 05 13 4 15 6 21 4 ...

Page 118: ...vable data rates in both uplink and downlink directions The numbers in the column of active slots are the total number of slots the GPRS device can use simultaneously for both uplink and downlink communications The description of different multi slot classes is shown in the following table Table 56 GPRS Multi slot Classes Multislot Class Downlink Slots Uplink Slots Active Slots 1 1 1 2 2 2 1 3 3 2...

Page 119: ...rdware Design SC606T_Series_Hardware_Design 118 116 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 ...

Page 120: ...eslot 2 Timeslot 4 Timeslot MCS 1 GMSK C 8 80 kbps 17 60 kbps 35 20 kbps MCS 2 GMSK B 11 2 kbps 22 4 kbps 44 8 kbps MCS 3 GMSK A 14 8 kbps 29 6 kbps 59 2 kbps MCS 4 GMSK C 17 6 kbps 35 2 kbps 70 4 kbps MCS 5 8 PSK B 22 4 kbps 44 8 kbps 89 6 kbps MCS 6 8 PSK A 29 6 kbps 59 2 kbps 118 4 kbps MCS 7 8 PSK B 44 8 kbps 89 6 kbps 179 2 kbps MCS 8 8 PSK A 54 4 kbps 108 8 kbps 217 6 kbps MCS 9 8 PSK A 59 2...

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