Smart Module Series
SC606T Series Hardware Design
SC606T_Series_Hardware_Design 61 / 116
The following is a reference design for dual camera application.
CSI2_CLK_N
78
AI
MIPI clock of front camera (-)
CSI2_CLK_P
77
AI
MIPI clock of front camera (+)
CSI2_LN0_N
80
AI
MIPI lane 0 data of front camera (-)
CSI2_LN0_P
79
AI
MIPI lane 0 data of front camera (+)
CSI2_LN1_N
82
AI
MIPI lane 1 data of front camera (-)
CSI2_LN1_P
81
AI
MIPI lane 1 data of front camera (+)
CSI2_LN2_N
84
AI
MIPI lane 2 data of front camera (-)
CSI2_LN2_P
83
AI
MIPI lane 2 data of front camera (+)
CSI2_LN3_N
86
AI
MIPI lane 3 data of front camera (-)
CSI2_LN3_P
85
AI
MIPI lane 3 data of front camera (+)
MCAM_MCLK
99
DO
Master clock of rear camera
1.8 V power domain.
SCAM_MCLK
100
DO
Master clock of front camera
1.8 V power domain.
MCAM_RST
74
DO
Reset of rear camera
1.8 V power domain.
MCAM_PWDN
73
DO
Power down of rear camera
1.8 V power domain.
SCAM_RST
72
DO
Reset of front camera
1.8 V power domain.
SCAM_PWDN
71
DO
Power down of front camera
1.8 V power domain.
CAM_I2C_SCL
75
OD
I2C clock of front and rear cameras
1.8 V power domain.
CAM_I2C_SDA
76
OD
I2C data of front and rear cameras
1.8 V power domain.
DCAM_MCLK
194
DO
Master clock of depth camera
1.8 V power domain.
CAM4_MCLK
236
DO
Master clock of fourth camera
1.8 V power domain.
DCAM_RST
180
DO
Reset of depth camera
1.8 V power domain.
DCAM_PWDN
181
DO
Power down of depth camera
1.8 V power domain.
DCAM_I2C_SDA
197
OD
I2C data of depth camera
1.8 V power domain.
DCAM_I2C_SCL
196
OD
I2C clock of depth camera
1.8 V power domain.
