Smart LTE Module Series
SC600Y&SC600T Hardware Design
SC600Y&SC600T_Hardware_Design 67 / 128
LCD_BL_A
21
PO
Current output for LCD
backlight
LCD_BL_K1
22
AI
Current sink for LCD
backlight
LCD_BL_K2
23
AI
Current sink for LCD
backlight
LCD_BL_K3
24
AI
Current sink for LCD
backlight
LCD_BL_K4
25
AI
Current sink for LCD
backlight
LCD0_RST
127
DO
LCD0 reset signal
Active low.
LCD0_TE
126
DI
LCD0 tearing effect signal
LCD1_RST
113
DO
LCD1 reset signal
Active low.
LCD1_TE
114
DI
LCD1 tearing effect signal
DSI0_CLK_N
116
AO
LCD0 MIPI clock signal
(negative)
DSI0_CLK_P
115
AO
LCD0 MIPI clock signal
(positive)
DSI0_LN0_N
118
AO
LCD0 MIPI lane 0 data
signal (negative)
DSI0_LN0_P
117
AO
LCD0 MIPI lane 0 data
signal (positive)
DSI0_LN1_N
120
AO
LCD0 MIPI lane 1 data
signal (negative)
DSI0_LN1_P
119
AO
LCD0 MIPI lane 1 data
signal (positive)
DSI0_LN2_N
122
AO
LCD0 MIPI lane 2 data
signal (negative)
DSI0_LN2_P
121
AO
LCD0 MIPI lane 2 data
signal (positive)
DSI0_LN3_N
124
AO
LCD0 MIPI lane 3 data
signal (negative)
DSI0_LN3_P
123
AO
LCD0 MIPI lane 3 data
signal (positive)
DSI1_CLK_N
103
AO
LCD1 MIPI clock signal
(negative)
DSI1_CLK_P
102
AO
LCD1 MIPI clock signal
(positive)
DSI1_LN0_N
105
AO
LCD1 MIPI lane 0 data
