Quectel SC600T-EM Series, Hardware Design

Page: 39 / 136

Smart LTE Module Series
SC600Y&SC600T Hardware Design
SC600Y&SC600T_Hardware_Design 38 / 128
CSI2_CLK_P 77 AI
MIPI clock signal of
front camera
(positive)
CSI2_LN0_N 80 AI
MIPI lane 0 data
signal of front camera
(negative)
CSI2_LN0_P 79 AI
MIPI lane 0 data
signal of front camera
(positive)
CSI2_LN1_N 82 AI
MIPI lane 1 data
signal of front camera
(negative)
CSI2_LN1_P 81 AI
MIPI lane 1 data
signal of front camera
(positive)
CSI2_LN2_N 84 AI
MIPI lane 2 data
signal of front camera
(negative)
CSI2_LN2_P 83 AI
MIPI lane 2 data
signal of front camera
(positive)
CSI2_LN3_N 86 AI
MIPI lane 3 data
signal of front camera
(negative)
CSI2_LN3_P 85 AI
MIPI lane 3 data
signal of front camera
(positive)
MCAM_MCLK 99 DO
Master clock signal of
rear camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_MCLK 100 DO
Master clock signal of
front camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
MCAM_RST 74 DO
Reset signal of rear
camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
MCAM_PWDN 73 DO
Power down signal of
rear camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_RST 72 DO
Reset signal of front
camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_PWDN 71 DO
Power down signal of
front camera V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.