Smart LTE Module Series
SC600Y&SC600T Hardware Design
SC600Y&SC600T_Hardware_Design 60 / 128
CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please
control the characteristic impedance of them as 50
Ω
, and do not cross them with other traces. It is
recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD,
DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding.
Layout guidelines:
⚫
Control impedance a
s 50Ω
±10%, and ground shielding is required.
⚫
The total trace length difference between CLK and other signal line traces should not exceed 1mm.
Table 15: SD Card Signal Trace Length Inside the Module
Pin No.
Signal
Length (mm)
Comment
70
SD_CLK
32.11
69
SD_CMD
32.11
68
SD_DATA0
32.11
67
SD_DATA1
32.11
66
SD_DATA2
32.11
65
SD_DATA3
32.11
3.13. GPIO Interfaces
SC600Y&SC600T have abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed
below.
Table 16: Pin Definition of GPIO Interfaces
Pin Name
Pin No.
GPIO
Default Status
Comment
GPIO_0
248
GPIO_0
B-PD:nppukp
1)
GPIO_1
247
GPIO_1
B-PD:nppukp
Wakeup
2)
GPIO_2
201
GPIO_2
B-PD:nppukp
GPIO_3
200
GPIO_3
B-PD:nppukp