Quectel LPWA Series, Hardware Design

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LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design 7 /89
Table Index
Table 1: Special Mark ................................................................................................................................................ 13
Table 2: Brief Introduction of BG950A-GL & BG951A-GL Modules .................................................................. 14
Table 3: Wireless Network Type .............................................................................................................................. 15
Table 4: Key Features ............................................................................................................................................... 16
Table 5: I/O Parameters Definition .......................................................................................................................... 20
Table 6: Pin Description ............................................................................................................................................ 21
Table 7: Overview of Operating Modes .................................................................................................................. 27
Table 8: Pin Definition of Power Supply ................................................................................................................. 31
Table 9: Pin Definition of PWRKEY ........................................................................................................................ 33
Table 10: Pin Definition of RESET_N ..................................................................................................................... 35
Table 11: Pin Definition of PON_TRIG ................................................................................................................... 37
Table 12: Pin Definition of (U)SIM Interface .......................................................................................................... 39
Table 13: Pin Definition of USB Interface .............................................................................................................. 41
Table 14: Pin Definition of PCM Interface .............................................................................................................. 43
Table 15: Pin Definition of I2C Interface ................................................................................................................ 43
Table 16: Pin Definition of Main UART Interface .................................................................................................. 44
Table 17: UART Information ..................................................................................................................................... 44
Table 18: Pin Definition of Debug UART Interface ............................................................................................... 45
Table 19: Pin Definition of Auxiliary UART Interface ........................................................................................... 45
Table 20: Pin Definition of ADC Interface .............................................................................................................. 46
Table 21: Characteristics of ADC Interface ........................................................................................................... 47
Table 22: Pin Definition of PSM_IND ..................................................................................................................... 47
Table 23: Pin Definition of NET_STATUS .............................................................................................................. 48
Table 24: Working State of Network Connection Status Indication .................................................................. 48
Table 25: Pin Definition of STATUS ........................................................................................................................ 49
Table 26: Pin Definition of MAIN_RI ....................................................................................................................... 50
Table 27: Default Behaviors of MAIN_RI ............................................................................................................... 50
Table 28: Pin Definition of GRFC Interface ........................................................................................................... 51
Table 29: Truth Table of GRFC Interface ............................................................................................................... 51
Table 30: Pin Definition of GPIO Interface ............................................................................................................ 51
Table 31: Pin Definition of Cellular Network Interface ......................................................................................... 53
Table 32: Operating Frequency of BG950A-GL & BG951A-GL ........................................................................ 53
Table 33: RF Output Power ...................................................................................................................................... 54
Table 34: Conducted RF Receiving Sensitivity of BG950A-GL ......................................................................... 55
Table 35: Conducted RF Receiving Sensitivity of BG951A-GL ......................................................................... 56
Table 36: Pin Definition of GNSS Antenna Interface ........................................................................................... 57
Table 37: GNSS Frequency ..................................................................................................................................... 58
Table 38: GNSS Performance ................................................................................................................................. 58
Table 39: Requirements for Antenna Design ........................................................................................................ 61
Table 40: Absolute Maximum Ratings .................................................................................................................... 65
Table 41: The Module’s Power Supply Ratings .................................................................................................... 65