PAC2514x Users Guide Preview
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Rev. 1.3 12 December 2023 © 2023 Qorvo US, Inc.
43 of 81
SOC.AFECTL1
Register 8-1
.
SOC.AFECTL1 (AFE Control 1, SOC 0x00)
BIT
NAME
ACCESS
RESET
DIFFAMP MODE
7
SRST
RW
0
Soft Reset
Write to 1 to reset the device. The majority of AFE registers will
be reset also unless noted.
This bit is self clearing and will always be read as 0.
6
MCUALIVE
RW
0
MCU Alive
This bit should be written to 1 by the MCU after it comes out of
reset. Prior to setting this bit, the AFE will only respond to SPI
transactions.
5
RFU
RW
0
Reserved, write as 0.
4
DIS_CPOK
RW
0
Charge Pump OK Overwrite
0: Normal Operation
1: Overwrite to OK
3
SCPDAC2VADC
RW
0
Mux Selection for Voltage SD ADC Ch20
0: Select BATOVDAC
1: Select SCPDAC
2
LOADDETEN
RW
0
Load Detect Enable
0: Disabled
1: Enabled
When enabled, measure PACK+ to determine if a load is present.
1
HVCPEN
RW
0
High Voltage Charge Pump Enable
0: Disabled
1: Enabled
0
SIGEN
RW
0
Signal Manager Tile Enable
0: disabled
1: enabled
