PAC2514x Users Guide Preview
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Rev. 1.3 12 December 2023 © 2023 Qorvo US, Inc.
53 of 81
SOC.PWRFAULT
Register 8-16
.
SOC.PWRFAULT (Power Fault, SOC 0x16)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7
RFU
R
0x0
Reserved
6
DRVFLT
W1C
0x0
Driver Fault Flag
5
VCCIOFLT
W1C
0x0
VCCIO Fault Flag
4
VDDAFLT
W1C
0x0
VDDA Fault Flag
3
VCOREFLT
W1C
0x0
VCORE Fault Flag
2
VSYSFLT
W1C
0x0
VSYS Fault Flag
1
VPFLT
W1C
0x0
VP Fault Flag
0
HVCPFLT
W1C
0x0
HVCP Fault Flag
SOC.TEMPFAULTEN
Register 8-17
.
SOC.TEMPFAULTEN (Temperature Fault Interrupt Enable, SOC 0x17)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:6
RFU
R
0x0
Reserved
5
TWARN2CBDEN
R/W
0x0
TWARN2 Cell
Balance Disable
–
If set to 1, then
when TWARN2
occurs, Cell Balancing
will be disabled
4
TWARN1CBDEN
R/W
0x0
TWARN1 Cell
Balance Disable
–
If set to 1, then
when TWARN1
occurs, Cell Balancing
will be disabled
3
RFU
R
0x0
Reserved
2
TMPFLTEN
R/W
0x0
Temperature Fault
Interrupt Enable
1
TWARN2EN
R/W
0x0
TWARN2 Fault
Interrupt Enable
0
TWARN1EN
R/W
0x0
TWARN1 Fault
Interrupt Enable
Note: This register requires a write of PROT_KEY before register can be written.
SOC.TEMPFAULT
Register 8-18
.
SOC.TEMPFAULT (Temperature Fault Flag, SOC 0x18)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7
TWARN2C_RTS
R/W
0x0
TWARN2 Real-Time
Status
6
TWARN1_RTS
R/W
0x0
TWARN1 Real-Time
Status
5:3
RFU
R
0x0
Reserved
2
TMPFLT
W1C
0x0
Temperature Fault
Flag
1
TWARN2
W1C
0x0
TWARN2 Fault Flag
0
TWARN1
W1C
0x0
TWARN1 Fault Flag
SOC.SIGFAULTEN
Register 8-19
.
SOC.SIGFAULTEN (Signal Manager Fault Interrupt Enable, SOC 0x19)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:6
RFU
R
0x0
Reserved
4
EMUXFLTEN
R/W
0x0
EMUX Fault Interrupt
Enable