PAC2514x Users Guide Preview
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Rev. 1.3 12 December 2023 © 2023 Qorvo US, Inc.
32 of 81
7.3
System Block Diagram
Figure 7-1 Configurable Analog Front End System Block Diagram
Configurable Analog Front End (CAFE)
-
+
ISNSP
CURRENT SENSE
+-
+
PROTECT
nIRQ
nPROT_DSG
ISNSN
OCD-COMP
OCC-COMP
-
+
16-bit
SD ADC
OCD-DAC
16-bit
SD ADC
CELL VOLTAGE SENSE
S
O
C
B
U
S
A
F
E
M
U
X
MCU Pin
VCC33
BAT
PACK+
VCP
VREF
FUSE
AFE MUX
CLKOUT
Low-speed Clock Source
VCORE
OCC-DAC
DA
VP
VSYS
VCCIO
CHG
DSG
VPTAT
PB
PUSH
BUTTON
Signal I/O
+
-
+
SCP-COMP
SCP-DAC
nPROT_CHG
Short Circuit
Protection
Discharge Onl
y
Over Current
Discharge
Protection
Over Current
Charge
Protection
V
B
M
U
X
VB1
VB20
...
PACK-
VSS
VADCCTL
IADCCTL
OCCDAC
OCDDAC
SCPDAC
EMUX
SPI
AFEMUXCTL.EMUX_EN
AFEMUXCTL.
BUFFEN
PB Pass
Through
AIO0
AIO0
AIO0A
PACK+
Charge/Load Detect
AFECTL1.LOADDETEN
HIBCTL.PACKWAKEEN
Charge
Detect
Load
Detect
Wake Up
Signals
SCPDAC
OCCDAC
OCDDAC
BATOVDAC
IM
U
X
Charge is P>N
OCCDAC
OCDDAC
SCPDAC
BATOVDAC
AFEMUXSEL
VIN
LOADDET
PBP TEN
...
-
BAT
PG6
S
O
C
B
U
S
...
MCU
12-bit
ADC
A
D
C
M
U
X
AD0
DTSE
ADCCTL.MODE
ADC
Registers
AD1
AD2
AD6
EMUX
AD7
...
...
A
D
2
AD
6
AD
7
AD
1
...
ISENSE
HVB_ISENSE
SCPDAC2VADC
G