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PAC2514x Users Guide Preview

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SOC.VADCCTL

SOC.VADCCTL (Voltage ADC Control, SOC 0x22)

BIT

NAME

ACCESS

RESET

DESCRIPTION

VADCSTART

R/W

0x0

Cell Voltage ADC
Start Conversion

VADCBUSY

0x0

Cell Voltage ADC
Busy
- This bit is set to 1
during conversion and
set to 0 when
complete.

RFU

Reserved

4:0

VBMUXSEL

R/W

0x0

Voltage ADC
MUX Select:

0: VB1
1: VB2
2: VB3
3: VB4
4: VB5
5: VB6
6: VB7
7: VB8
8: VB9
9: VB10
10: VB11
11: VB12
12: VB13
13: VB14
14: VB15
15: VB16
16: VB17
17: VB18
18: VB19
19: VB20
20:

BATOVDAC or

SCPDAC (see
AFECTL1)

21 - 31: RFU

SOC.VADCRESHI

SOC.VADCRESHI (Voltage ADC Result High, SOC 0x23)

BIT

NAME

ACCESS

RESET

DESCRIPTION

7:0

VADCRES[15:8]

Voltage ADC Result
MSByte

Summary of Contents for PAC2514 Series

Page 1: ...attery Management PRODUCT USER GUIDE 1 of 81 PAC2514x User Guide Preview PAC Battery Management System Multi Mode Power ManagerTM Configurable Analog Front EndTM Application Specific Power DriversTM A...

Page 2: ...ption 11 4 3 USART Configuration 12 4 4 Protocol 12 4 5 Write Register Example 12 4 6 Read Register Example 14 5 PAC2514X IO 15 5 1 Overview 15 5 2 ADC Channels 16 5 3 Digital Peripheral Pins 17 6 CON...

Page 3: ...suring Independent Cell Voltages 36 7 4 11 AFE MUX 37 7 4 12 Enabling the CAFE 38 7 4 13 Push Button PB Input 38 7 5 Analog I O 0 AIO0 39 7 5 1 AIO0 Block Diagram 39 8 Miscellaneous AFE Registers and...

Page 4: ...er Access 11 Figure 4 2 Analog Peripheral Register Write Timing 12 Figure 4 3 Analog Peripheral Register Read Timing 14 Figure 5 1 GPIO and DPM Block Diagram 15 Figure 6 1 Power Manager System Block D...

Page 5: ...ember 2023 2023 Qorvo US Inc 5 of 81 LIST OF TABLES Table 5 1 PAC2514X ADC Input Pins 16 Table 5 2 PAC2514X Internal Connections 16 Table 5 3 PAC2514X Digital Peripheral Pins 17 Table 6 1 CPM Register...

Page 6: ...Register 8 13 SOC PROTEN Reset Status SOC 0x13 50 Register 8 14 SOC FUSE Fuse Driver Control SOC 0x14 51 Register 8 15 SOC PWRFAULTEN Power Fault Interrupt Enable SOC 0x15 52 Register 8 16 SOC PWRFAU...

Page 7: ...40 SOC CFGCB2 Configure Cell Balance 2 SOC 0x34 62 Register 8 41 SOC CFGCB3 Configure Cell Balance 3 SOC 0x35 62 Register 8 42 SOC GP General Purpose Register SOC 0x40 62 Register 8 43 SOC CLKOUTCFG C...

Page 8: ...onsent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 8 of 81 1 OVERVIEW This document is the PAC2514x Device User Guide It details the operation of the analog peripherals in the PAC25140 PA...

Page 9: ...as a postfix For example 1011b binary Bh hexadecimal 11 decimal 2 2 Formatting Styles TYPE EXAMPLE DESCRIPTION Register Name RTCCTL Register names use a capital letter and boldface type Register Bit s...

Page 10: ...40 Power Application Controller PX Y DEBUG ETM ARM CORTEX M4F CORE TIMERS 4 DEAD TIME 16 PWM CC 32 PWM ENGINE PX Y PX Y PX Y PX Y PX Y BRIDGE WWDT DTSE DATA ACQUISITION AND SEQUENCER 12 BIT ADC MUX 1k...

Page 11: ...two register buses the AHB bus and the APB bus The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory Controller To access other digital peripheral connected to the APB bus...

Page 12: ...high CPH is sample setup SS active low When communicating with the Analog Peripherals the maximum SCLK frequency is 25MHz 4 4 Protocol The protocol for communicating with the Analog Peripherals is a...

Page 13: ...PAC2514x Users Guide Preview No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 13 of 81...

Page 14: ...sue the following transactions to USART A Write SSPADAT with the value 22h 11h 1 0b for read transaction Write SSPADAT with a dummy character Read last data from MISO from SSPADAT this is the register...

Page 15: ...ins Each member of the family has a different set of IO pins that are available It is important during application design that the designer consider the available IO pins to make sure the necessary pe...

Page 16: ...PD2 PG6 Package pin AD3 PD1 Package pin AD4 PD0 PF4 Package pin AD5 PF5 Package pin AD6 PF6 Package pin AD7 PF7 Package pin Table 5 2 PAC2514X Internal Connections AFE Function MCU I O PIN Description...

Page 17: ...PWM2 TBPWM2 P4 GPIOB4 TAPWM4 TBPWM4 P5 GPIOB5 TAPWM5 TBPWM5 P6 GPIOB6 TAPWM6 TBPWM6 GPIOC P4 GPIOC4 TBPWM4 TCPWM4 TCIDX USBMOSI USCSCLK CANRXD I2CSCL P5 GPIOC5 TBPWM5 TCPWM5 TCPHA USBMISO USCSS CANTXD...

Page 18: ...without Qorvo s prior written consent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 18 of 81 P5 GPIOF5 TCPWM5 TDPWM5 TCPHA USDSS EMUXD P6 GPIOF6 TCPWM6 TDPWM6 TCPHB USDMOSI CANRXD I2CSCL Fo...

Page 19: ...5V VREF POWER TEMP MON VMON VTEMP HIGH VOLTAGE BUCK CONTROLLER HV BUCK ERROR AMP COMP CURR LIMIT ERROR COMP START UP MODE CTRL PWM LOGIC CLAMP DRIVER DRM MUX CURR SENSE CSM SRC BST 1 2V REG 5V_INT LI...

Page 20: ...motor is not running and the battery pack need not provide power See control registers in Register 8 6 To enter hibernate mode configure the SOC HIBCTL register settings and the set SOC HIBENTER HIB t...

Page 21: ...nd Faults The PAC2514X has an integrated temperature sensor that is used for temperature warnings and faults and can also be sampled by the MCU ADC through the AFE MUX using the VPTAT MUX channel This...

Page 22: ...ritten consent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 22 of 81 There is not interrupt for this condition When the device falls below the hysteresis value then the DC DC will be re en...

Page 23: ...ION 7 TMPWARN R 0x0 Real time temperature warning status When the temperature is greater than the warning threshold this bit is set to 1b When the temperature less than the warning threshold this bit...

Page 24: ...December 2023 2023 Qorvo US Inc 24 of 81 2 VCCIOFLT R 0x0 VCCIO fault Set on fault and cleared when written to 1b 0b No VCCIO fault 1b VCCIO fault 1 VCC33FLT R 0x0 VCC33 fault Set on fault and cleare...

Page 25: ...Watchdog Timer Reset Status When enabled this bit is set on Watchdog Timer Reset and cleared when written to 1b 0b No WDT reset 1b WDT Reset 4 RFU R 0x0 Reserved 3 VPLOW R 0x0 Real time VP Low Status...

Page 26: ...utton Enable 0b Push button not enabled 1b Push button enabled 5 VREFSET R W 0x0 ADC Reference Voltage Setting 0b 2 5V 1b 3 0V 4 CLKOUTEN R W 0x0 Low speed clock output CLKOUT enable 0b Not enabled 1b...

Page 27: ...RESET DESCRIPTION 7 6 CLKOUTFREQ R W 0x0 Low Speed Clock Output Frequency Setting CLKOUT 00b 250Hz 01b 500Hz 10b 1kHz 11b 2kHz 5 3 PWRMON R W 0x0 Power Monitor Signal This field selects the signal to...

Page 28: ...d for writing when UNLOCK 1b BIT NAME ACCESS1 RESET DESCRIPTION 7 RFU R W 0x0 Reserved 6 nTMPWARN R W 0x0 Temperature Warning Mask 0b Masked 1b Not masked asserts nIRQ1 5 nVPFLT R W 0x0 VP Fault Mask...

Page 29: ...DESCRIPTION 7 SRST R W 0x0 Soft Reset This bit can be set to issue a system soft reset This bit is always read as 0b When set the STATUS SRST bit will be latched to a 1b so the MCU knows the system is...

Page 30: ...Rev 1 3 12 December 2023 2023 Qorvo US Inc 30 of 81 6 5 7 SOC SYSCONF Register 6 7 SOC SYSCONF System Configuration 2Bh BIT NAME ACCESS RESET DESCRIPTION 7 4 RFU R 0x0 Reserved 3 VPSET R W 0x1 VP Sett...

Page 31: ...MUX which contains inputs for each of the cell balance channels Internal power supply rails temperature and other signals can be selected using the AFE Mux and sampled using the MCU 12 bit SAR ADC 7...

Page 32: ...ow speed Clock Source VCORE OCC DAC DA VP VSYS VCCIO CHG DSG VPTAT PB PUSH BUTTON Signal I O SCP COMP SCP DAC nPROT_CHG Short Circuit Protection Discharge Only Over Current Discharge Protection Over C...

Page 33: ...er is connected to the 16 bit Sigma Delta ADC for current sensing and also to over current protection comparators 7 4 3 IADC 16 bit Sigma Delta ADC The IADC is a 16 bit Sigma Delta ADC and has an inpu...

Page 34: ...termining which source asserted the IRQ signal can be achieved by reading the SOC SIGFAULT register 7 4 5 Short Circuit Protection Short Circuit protection SCP is designed to disable gate drivers if t...

Page 35: ...CFAULT flag is cleared by writing a 1d Over current charge protection comparator output can be polled in real time by reading the SOC BATRTS OCC_RTS bit When OCCDAC OCDDAC are selected to IADC IMUX th...

Page 36: ...OC SIGMGRCTL1 BATOVEN bit The BATOV comparator blanking time can be configured by writing the SOC BATOVCFG register The hysteresis is not configurable and is fixed Once the BATOV DAC value is exceeded...

Page 37: ...l Voltage conversion can be obtained by reading the SOC VADCRESHI and SOC VADCRESLO registers Reading cell voltages can be achieved concurrently while the current ADC operates and convert current valu...

Page 38: ...evice The push button polarity can be set to active high or active low using the polarity setting The push button module can be configured so that an active PB will wake up the PAC2514X from hibernate...

Page 39: ...of the gain amplifier AIO0A routed to the AFE Mux for input to the MCU ADC Or the AIO0 pin can be configured to output internal signals of the AFE The following signals are available for output on th...

Page 40: ...AFE Registers and Controls 8 1 General Purpose Register The device contains an 8 bit general purpose register in the analog sub system that is available for user applications This register may be use...

Page 41: ...ush Button 0x09 AIO0CFG AIO 0 Configuration 0x10 PROTKEY Protection Key 0x11 SIGMGRCTL1 Signal Manager Control 1 0x12 SIGMGRCTL2 Signal Manager Control 2 0x13 PROTEN Protection Enable 0x14 FUSE Fuse D...

Page 42: ...tion DAC 0x2B OCCCFG Over Current Charge Protection Configuration 0x2C OCCDAC Over Current Charge Protection DAC 0x2D OCDCFG Over Current Discharge Protection Configuraiton 0x30 CELLEN1 Cell Enable 1...

Page 43: ...d will always be read as 0 6 MCUALIVE RW 0 MCU Alive This bit should be written to 1 by the MCU after it comes out of reset Prior to setting this bit the AFE will only respond to SPI transactions 5 RF...

Page 44: ...ve SOC AFEMUXCTL Register 8 3 SOC AFEMUXCTL AFE Mux Control SOC 0x03 BIT NAME ACCESS RESET DESCRIPTION 7 2 RFU R 0 Reserved 1 BUFFEN RW 0x0 ADC Buffer Enable 0 Disabled 1 Enabled Enables the buffer af...

Page 45: ...81 4 0 AFEMUXSEL R W 0x0 AFE MUX Channel Selector 0 VCORE 1 VCORE 2 5 2 VDDA 2 5 3 VCCIO 2 5 4 VSYS 2 5 5 ISENSE 6 VPTAT 7 VP 10 8 VREF 2 9 FUSE 10 10 CHG 50 11 DSG 50 12 BAT 50 13 AIO0A 14 LOADDET 1...

Page 46: ...Timer Duration 0 Disabled 1 125ms 2 250ms 3 500ms 4 1s 5 2s 6 4s 7 8s 4 3 WAKESRC R W 0x0 Wake Up Source 0 PB 1 PACK 2 WUTIMER 3 RFU 2 PACKWAKEVREF R W 0x0 PACK Wake Up Voltage Reference Threshold 0...

Page 47: ...nd has been active for 8 seconds 3 HIBRST W1C 0x0 Hibernate Reset Flag This flag will be set when the device has been reset following a hibernate wake up Read the HIBCTL WAKESRC bits to determine the...

Page 48: ...errupt Flag 5 PBINTEN R W 0x0 Push Button Interrupt Enable The interrupt is level sensitive 4 PBPOL R W 0x0 Push Button Polarity 0 Active Low 1 Active High Depending on other bit settings an active si...

Page 49: ...XOUT 2 IMUXOUT 3 VBMUXOUT 15 4 RFU 4 RFU R W 0x0 Reserved 3 2 SWAP R W 0x0 Swaps the offset of the buffer 0 No swap 1 Swap 1 MODE R W 0x0 AIO0 Buffer Mode 0 Input Buffer Mode 1 Output Buffer mode 2mA...

Page 50: ...SIGMGRCTL2 Register 8 12 SOC SIGMGRCTL2 Signal Manager Control 2 SOC 0x12 BIT NAME ACCESS RESET DESCRIPTION 7 3 RFU R 0x0 Reserved 2 PBPTEN R W 0x0 Push Button Pass Through Enable 1 IADCEN R W 0x0 Cur...

Page 51: ...then when protection is activated the DSG FET will be disabled Note This register requires a write of PROT_KEY before register can be written SOC FUSE Register 8 14 SOC FUSE Fuse Driver Control SOC 0x...

Page 52: ...0x15 BIT NAME ACCESS RESET DESCRIPTION 7 RFU R 0x0 Reserved 6 DRVFLTEN R W 0x0 Driver Fault Interrupt Enable 5 VCCIOFLTEN R W 0x0 VCCIO Fault Interrupt Enable 4 VDDAFLTEN R W 0x0 VDDA Fault Interrupt...

Page 53: ...to 1 then when TWARN2 occurs Cell Balancing will be disabled 4 TWARN1CBDEN R W 0x0 TWARN1 Cell Balance Disable If set to 1 then when TWARN1 occurs Cell Balancing will be disabled 3 RFU R 0x0 Reserved...

Page 54: ...2023 2023 Qorvo US Inc 54 of 81 3 SCPFLTEN R W 0x0 Short Circuit Protection Fault Interrupt Enable 2 OCCFLTEN R W 0x0 Over Current Charge Fault Interrupt Enable 1 OCDFLTEN R W 0x0 Over Current Dischar...

Page 55: ...protections trips and disables the CHG FET This bit must be written with a 1 to clear it before the CHG FET can be enabled again 5 DSGFLT W1C 0x0 DSG Fault Flag This flag will be set if a DSG Protect...

Page 56: ...me Status SOC BATOVCFG Register 8 22 SOC BATOVCFG Battery Over Voltage Comparator Config SOC 0x20 BIT NAME ACCESS RESET DESCRIPTION 7 4 BLANKSF R W 0x0 Blanking Scale Factor 0 1 1 2 2 3 14 15 15 16 3...

Page 57: ...e ADC Start Conversion 6 VADCBUSY R 0x0 Cell Voltage ADC Busy This bit is set to 1 during conversion and set to 0 when complete 5 RFU R 0 Reserved 4 0 VBMUXSEL R W 0x0 Voltage ADC MUX Select 0 VB1 1 V...

Page 58: ...Y R 0x0 Current ADC Busy This bit is set to 1 during conversion and set to 0 when complete 5 RFU R 0 Reserved 4 3 IMUXSEL 1 0 R W 0x0 0 Isense Diff Amp Output 1 SCP DAC 2 OCC DAC 3 OCD DAC 2 0 DAGAIN...

Page 59: ...CESS RESET DESCRIPTION 7 4 BLANKSF R W 0x0 Blanking Scale Factor 0 1 1 2 2 3 14 15 15 16 3 0 TIMEBASE R W 0x0 Time Base 0 1uS 1 2uS 2 4uS 3 256uS 15 32768 uS Notes This register requires a write of PR...

Page 60: ...F 2 So Blanking Time 2uS 3 6uS OCD Comparator Hysteresis is fixed at 25mV SOC OCCDAC Register 8 34 SOC OCCDAC OCC DAC SOC 0x2C BIT NAME ACCESS RESET DESCRIPTION 7 0 OCCDAC RW 0 OCC DAC Setting This is...

Page 61: ...Cell 3 Enable 1 CEN2 R W 0x0 Cell 2 Enable 0 CEN1 R W 0x0 Cell 1 Enable SOC CELLEN2 Register 8 37 SOC CELLEN2 Cell Enable 2 SOC 0x31 BIT NAME ACCESS RESET DESCRIPTION 7 CEN16 R W 0x0 Cell 16 Enable 6...

Page 62: ...CFGCB2 Configure Cell Balance 2 SOC 0x34 BIT NAME ACCESS RESET DESCRIPTION 7 VB16 R W 0x0 Cell 16 Cell Balance Enable 6 VB15 R W 0x0 Cell 15 Cell Balance Enable 5 VB14 R W 0x0 Cell 14 Cell Balance Ena...

Page 63: ...Low Speed Clock Output Enable Note Used during clock test that can help meet Class B Safety SOC WWDTCTL Register 8 44 SOC WWDTCTL Windowed Watchdog Timer Control SOC 0x42 BIT NAME ACCESS RESET DESCRIP...

Page 64: ...Windowed Watchdog Timer Window SOC 0x45 BIT NAME ACCESS RESET DESCRIPTION 7 0 WINDOW 7 0 RW 0x0 WWDT Window Value If WWDTRST is written when CTR WINDOW then the WWDT will issue a device reset SOC WWD...

Page 65: ...CHG and DSG FETs is VCP BAT 9V The FUSE output is a low side switch supplied by VP which is intended for driving the gate on an external FET which is used to blow an external fuse in series with PACK...

Page 66: ...ev 1 3 12 December 2023 2023 Qorvo US Inc 66 of 81 PROTEN register These protections control the nPROT_CHG and nPROT_DSG signals that disable the gate drivers when active 8 3 2 Detail Block Diagram DS...

Page 67: ...res Cell Balancing FETs for up to 20 cells Allows for discharge of individual cells Voltage ADC for sensing the voltage of each cell 8 4 1 Block Diagram SOC BUS VB20 CFGCB3 VB20 VB MUX CFGCB3 VB19 VB2...

Page 68: ...pling from the 16 bit ADC Adjacent cells should not be balanced at the same time In the event that too many cells are being balanced at the same time and Thermal protection occurs then the cell balanc...

Page 69: ...pin AD4 PC4 Package pin AD5 PC5 Package pin AD6 PC6 Package pin The AD0 channel is always used for analog input from the AFE and is connected to the AFE MUX on MCU internal pin PG7 ADC channels AD 6 2...

Page 70: ...13 Analog Input Output 0 Amp Output LOADDET 14 Load Detection Voltage SCPDAC 15 SCP DAC Voltage OCCDAC 16 OCC DAC Voltage OCDDAC 17 OCD DAC Voltage BATOVDAC 18 BAT Over Voltage DAC VIN 19 VIN 50 PACK...

Page 71: ...8 49 EMUX Packet Structure BIT NAME DESCRIPTION 7 BIT7 Bit 7 should be set to 0b 6 BIT6 Bit 6 should be set to 1b 5 BIT5 Bit 5 should be set to 0b 4 0 AFEMUXSEL AFE MUX Channel Selector 0 VCORE 1 VCOR...

Page 72: ...e 8th EMUX clock falling edge the AFE will read the AFEMUXSEL 4 0 data At this time the AFE will set the AFE MUX to the proper channel according to this data 8 5 3 High Voltage Signal EMUX Correction...

Page 73: ...Interrupt Controller WIC included Sleep Mode power saving included Little Endian configuration 24 bit SysTick timer included Embedded Trace Module ETM included o Instruction trace only ARM provides a...

Page 74: ...of 81 9 1 PAC25xxx Architecture Figure 9 1 Top Level Block Diagram PAC SOC BUS Power Application Controller 128kB FLASH 32kB SRAM CLOCK CONTROL RTC Calendar GPIO USART 3 I2C CAN SYSTEM CONTROL APB AHB...

Page 75: ...es 9 2 2 Features Clock Control System CCS o 4 clock sources 4MHz internally generated 2 RC oscillator 16MHz Ring Oscillator External clock input for up to 20MHz external clock sources Crystal driver...

Page 76: ...Preview No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 76 of 81 Figure 9 2 Clock Co...

Page 77: ...view No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 3 12 December 2023 2023 Qorvo US Inc 77 of 81 9 3 MCU MEMORY MAP Figu...

Page 78: ...F is 1995695Hz 0010 042Ch CLKREF CLKREF is measured FCLK_Post CLKREF 40 Value of CLKREF FCK_Post 40 1000 Example 99 5609 40 1000 3982436Hz 0010 0430h RESERVED 0010 0434h VREF RESERVED Value of ADCREF_...

Page 79: ...4ACh VB20ADCAL VB20 Gain and Offset Calibration 0010 04B0h IADCAL1X_Gain Gain calibration of IADC_1x iadc1x_gain 0010 04B4h IADCAL1X_Offset Offset calibration of IADC_1x iadc1x_offset 0010 04B8h 04ECh...

Page 80: ...com Rev 1 3 12 December 2023 2023 Qorvo US Inc 80 of 81 10 Revision History Revision DESCRIPTION 1 0 PAC2514X Preview Release 1 1 Align format to PAC22140 Updated BATDACOV 2 1 2 Updated EMUX table ASP...

Page 81: ...regard to such Users Guide Information itself or anything described by such information USERS GUIDE INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN AND QORVO...

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