FL0054601-00 B
A-1
Appendix A
Compliance, Specifications, and Agency Certification
A.1
Compliance
■
PCI-X Addendum
(revision 1.0a) to the
PCI Local Bus Specification
revision 2.2
■
PCI Hot Plug Specification
revision 1.0
■
PCI Bus Power Management Interface Specification
rev 1.1
■
Second Generation FC Generic Services Definition
(FC-GS-2)
■
Third Generation FC Generic Services Definition
(FC-GS-3)
■
Fibre Channel-Physical and Signaling Interface
(FC-PH)
■
SCSI-3 Fibre Channel Protocol
(SCSI-FCP)
■
Fibre Channel-Arbitrated Loop-2
(FC-AL-2)
■
Fibre Channel-Private Loop Direct Attach Technical Report
(FC-PLDA)
■
Fibre Channel Framing and Signaling
(FC-FS)
■
Compliance with U.S. and international safety and emissions standards
A.2
Specifications
Tables
define the QLA200
specifications.
Table A-1. QLA200 Board Specifications
Type
Specification
Host bus
Conforms to
PCI Local Bus Specification
, revision 2.2 and the
PCI-X Addendum
, revision 1.0a
PCI/PCI-X signaling
environment
3.3 V and 5.0 V buses supported
PCI/PCI-X transfer
rate
132 MBps maximum burst rate for 32-bit PCI operation at 33 MHz
264 MBps maximum burst rate for 32-bit PCI/PCI-X operation at
66 MHz
Fibre Channel
specifications
Bus type:
Multimode fibre optic media
Bus transfer rate: 200 MBps maximum at half-duplex
400 MBps maximum at full-duplex, 2-Gbps
CPU
Single-chip design that includes a QLogic RISC processor, Fibre
Channel protocol manager, PCI/PCI-X DMA controller, and
integrated serializer/deserializer (SERDES) and electrical
transceivers that operate at a fixed data rate of 2 Gbps
RAM
256 KB of sync SRAM supporting parity protection
BIOS ROM
128 KB of flash ROM in two 64-KB, software selectable banks.
The flash is field programmable.
