QDI P6I440EX/MATX EXCELLENT II, Manual

Page: 37 / 52

Chapter 3
3 -
7
ROM PCI/ISA BIOS (2A69JQ1K)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration : Enabled SDRAM CAS latency Time : 3
DRAM Speed Selection : 60ns
MA Wait State : Slow
EDO RAS # TO CAS# Delay : 3
EDO RAS # Time : 3
EDO DRAM Read Burst : X333
EDO DRAM Write Burst : X222
DRAM ECC Select : Disabled
CPU- TO -PCI IDE Posting : Enabled
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Disabled
Video RAM Cacheable : Disabled
8 bit I/ O Recovery Time : 1
16 bit I/ O Recovery Time : 1
Memory Hole At 15M-16M : Disabled
Passive Release : Enabled
Delayed Transaction : Enabled
ESC: Quit
↑↓→←
: Select Item
AGP Aperture Size (MB) : 64 F1: Help PU/PD/+/- : Modify
SDRAM RAS- to - CAS Delay : Slow F5: Old Values (Shift)F2: Color
SDRAM RAS
Time : Slow F7: Load Setup Defaults
Figure-5 Chipset Features Setup Menu
The following indicates the options of each item and describes their meaning.
Item Option Description
•
Auto Configuration
Enabled Automatically configures DRAM Timing according
to the value of “DRAM Speed Selection”.
Disabled
Manually configure.
Note: It is recommended that the “Enabled”
option be chosen by common users.
•
DRAM Speed
Selection
50ns,
60ns This item is of selected EDO DRAM read/write timing. You
must ensure that your DIMMs are as fast as 50ns, otherwise
60ns should be selected.
•
MA Wait State Slow
Fast
One additional wait state is inserted before the
assertion of the first MA and CAS#/RAS# during
DRAM read or write leadoff cycles. This affects
page hit, row miss and page miss cases.
Without additional wait state.
•
EDO RAS# To
CAS# Delay
2 Adds a delay time between the assertion of RAS#
and CAS#
3 Without additional delay time.
•
EDO RAS#
Time
3
4 DRAM RAS# time=3x system clocks.
DRAM RAS# time=4x system clocks.
•
EDO DRAM Read
Burst
×
3 3 3,
×
2 2 2,
The DRAM read burst timing depends on the type
of DRAM on a per-row basis. Slower rates may be
required to support slower DRAM.