Owner’s Reference
DirectStream DAC
4826 Sterling Drive, Boulder, CO 80301
PH: 720.406.8946 [email protected] www.psaudio.com
Introduction iv
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©2014 PS Audio Inc. All rights reserved.
Introduction
DirectStream is entirely DSD based, even for PCM inputs. DSD was chosen as
the core engine for this instrument for a number of compelling reasons:
•
DSD is simple to convert to analog: just low pass filter it.
•
DSD is inherently linear: it’s hard to build a PCM DAC that always
takes the same sized step in the output for any possible unit increment
of the representative PCM voltage value. The best PCM technology
for linearity is arguably a resistor ladder, then all steps are at least
positive for a positive change in the input, but making resistors that are
accurate to one part in 2
16
is hard and to one part in 2
20
very hard. DSD
doesn’t need anywhere near this level of component matching.
•
DSD soft clips when overdriven, more like magnetic tape: signals which
exceed the nominal full scale value only get slightly compressed if at
all. With PCM you either have flat tops which induce extra energy at
the squared off edges or, worse, you can have wrap around, which is
very audible.
•
All bits in a DSD stream have the same weight: a single bit error
anywhere is barely measurable let alone audible. Some bits in PCM
carry a lot of weight and would make a very loud pop if changed. PCM
needs more error recovery to keep to a given signal to noise ratio (S/N)
with a slightly corrupted digital signal.
•
Ironically, most sanely priced PCM players actually use DAC chips that
utilize a sigma-delta modulator (DSD) to get a DSD-ike signal anyway.
Similarly many (most) A/Ds are sigma-delta based. The typical PCM
path is analog -> DSD -> PCM -> disc -> PCM -> DSD -> analog.
The DSD path can skip the conversions to PCM. Those conversions
can’t be perfect and artifacts of the steep anti-aliasing filter or the
reconstruction filter aren’t considered benign by many.
•
DiectStream handles the PCM conversion from AES/EBU, S/PDIF,
TOSLINK, I
2
S and USB without recovering a clock, by simply watching
for the edges and making decisions about what they mean in context.
The result is that any jitter present on the input is lost entirely in the
FPGA. There is no difference in TOSLINK or I
2
S because the output
clock’s rate only depends on the long term average rate of the inputs
not on any edge or other local feature.
Why DSD?
