Chapter 5 - System Setup
5-7
PL-5900 Series User Manual
Select Advanced Chipset Features from the Main Menu and the following screen
will appear.
5.2.4 Advanced Chipset Features
Advanced DRAM Control 1
Press Enter
PCI Peer Concurrency
Enabled
Read Prefetch Memory RD
Enabled
Assert TRDY After Prefet
1 QWs
CPU to PCI Burst Mem. WR
Enabled
AGP Aperture Size
64MB
Graphic Window WR Combin
Enabled
System BIOS Cacheable
Enabled
Video BIOS Cacheable
Enabled
Memory Hole at 15M-16M
Disabled
PCI Post Write Buffer
Enabled
L2 Cache WT/WB Policy
W B
Memory Parity Check
Enabled
↑↓→←
:
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
IDE Primary Master
Item Help
Menu Level
Advanced DRAM Control 1
These selections display the DRAM setting. Press [Enter] to display the setting item
menu. The available settings are [100MHz] or [Manual]. The factory default setting
is [100MHZ] and is recommended for most users.
PCI Peer Concurrency
This setting determines if the CPU will use L2/DRAM in parallel with PCI-to-PCI
access. The available settings are [Disabled] and [Enabled]. The factory default
setting is [Enabled] and is recommended for most users.
Read Prefetch Memory RD
This setting determines if the Memory Read command is used by the chipset to
prefetch data. The available settings are [Disabled] and [Enabled]. The factory
default setting is [Enabled] and is recommended for most users.
Assert TRDY After Prefet
This setting determines the TRDY assert data used for memeory processing by the
chipset. The available settings are [2QWs] and [1QWs]. The factory default
setting is [1QWs] and is recommended for most users.
CPU to PCI Burst Mem. WR
The setting determines whether the PCI write buffer is used. The write buffer is
not used when the [Disabled] option is selected. The available settings are [Dis-
abled] and [Enabled]. The factory default setting is [Enabled] and is recom-
mended for most users.
