PowerTek PA2553, User Manual, Page: 14 / 88

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PA2553
User's Guide
The DSP generates a Sample-Clock signal from the computed frequency of the
user-selected synchronization source. The Sample-Clock signal clocks the
ADCs at a suitable frequency to ensure exact synchronization of the overall
measurements to the applied signals. The sampling frequency may be up to
170KHz and is slightly "dithered" to ensure that individual samples cannot be at
the exact same phase of the applied signals, while maintaining exact
synchronization for the overall measurement period.
The samples read from the FIFOs are passed through one to three stages of 6-
pole elliptical filters. (The stage of filtering is dependent on user-selected
configuration and bandwidth of harmonics measurements.) The first stage
filters the samples for all nonharmonic measurements. The second stage is anti-
alias filtering of the samples for the DFT and waveform collection. The third
stage filters the samples for waveform period measurements to display the
synchronized results.
All measurements are made nominally over four cycles of the applied signal and
then two-pole filtered with a user-selected "averaging" filter to produce fast, yet
stable, measurement results. (Note that there are more cycles at very high
frequencies and less at very low frequencies.)
Historical results are maintained by the DSP from the unfiltered measurement
results. Harmonics results, both amplitude and phase, are computed by the DSP
by means of a variable length Discrete Fourier Transform (DFT). Nominally
400 equally spaced samples per cycle are also collected for waveform display
purposes.
At nominal line frequencies and below, all measurements are continuous, there
being no missed portions of the signal in any of the resultant measurements. At
very high frequencies "gaps" can only result in the harmonics measurements.
The DSP also contains 4Kx24 of internal RAM for working memory, 3Kx24 of
program memory and a 1Kx24 level 1 cache memory.
The DSP can perform one arithmetic and two data movements per 12.5ns,
yielding 80MIPs for arithmetic operations and 240MIPs overall capability.
IEEE488 Interface —Performs the majority of the bus interface details for the IEEE488
protocol. All IEEE-448 interfacing is with data output from the DSP, or data
and commands input to the DSP. This interface is controlled using a
commercially available IC (National Instruments TNT488).
Parallel Printer Interface —This IC performs the majority of the bus interface details
for the parallel printer protocol. The data to be output over the interface comes
from the DSP. This interface is controlled using a commercially available IC.
Graphical Display Module —Allows a visual reading of the results in alphanumeric
and/or graphical format. The display screen is a commercially available LCD
with 240x64 pixels and a CCD backlight. All graphical information for the
screens is generated by the DSP.