PLX Technology PEX 8632-AA, Quick Start Manual

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PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
vi © 2007 PLX Technology, Inc. All Rights Reserved.
Figures
Figure 1. Sample PCI Express Link Block Diagram ..................................................................................... 2
Figure 2. Single-Ended versus Differential Voltage...................................................................................... 3
Figure 3. Transport Delay Delta ................................................................................................................... 7
Figure 4. PEX 8632 RefClk Circuitry ............................................................................................................ 7
Figure 5. Enable NT Function with NT Strapping Balls ................................................................................ 8
Figure 6. Disable NT Function with NT Strapping Balls ............................................................................... 8
Figure 7. PHPC Circuit Block Diagram......................................................................................................... 9
Figure 8. SHPC Interface to PEX 8632 Block Diagram.............................................................................. 10
Figure 9. JTAG Interface Block Diagram.................................................................................................... 11
Figure 10. I
2
C Interface Block Diagram ...................................................................................................... 12
Figure 11. Power Balls and Capacitor Placement...................................................................................... 17
Figure 12. Power Plane Impedance versus Frequency ............................................................................. 19
Figure 13. Capacitor Footprint Effects on Series Inductance..................................................................... 20
Figure 14. Top Layer BGA Layout and Routing Escape ............................................................................ 22
Figure 15. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement ........................... 22
Figure 16. Add-In Board Routing to PCI Express Gold Fingers ................................................................. 23
Figure 17. System Board Routing to PCI Express Slot .............................................................................. 23
Figure 18. PCI Express Midbus Routing Example ..................................................................................... 24
Tables
Table 1. Receiver Equalization Settings....................................................................................................... 5
Table 2. PEX 8632 LED On/Off Patterns, by State .................................................................................... 12
Table 3. Configuration Strapping Balls – 8-Port Mode ............................................................................... 13
Table 4. Active Lanes – 8- and 12-Port Modes .......................................................................................... 14
Table 5. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 8-Port Mode .. 14
Table 6. Configuration Strapping Balls – 12-Port Mode ............................................................................. 15
Table 7. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 12-Port Mode 16