PLX Technology PEX 8632-AA, Quick Start Manual

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PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved.
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1.1.2 Receiver
The Receiver’s role is to recover the differential bitstream coming across the Channel from the
Transmitter, and latch it so it can be de-serialized and forwarded to the logical sub-block. The main
components of a Receiver are the Receive buffer and CDR circuit.
The PCI Express Receive buffer input threshold is 175 mV for a 2.5 GT/s data rate and 120 mV for
a 5.0 GT/s data rate. PCI Express Receivers are required to have a DC common mode voltage of 0V.
The Receive buffer provides bits to the CDR circuit, which samples each bit and forwards them to the
de-serializer. Digital-based CDRs must track the edges of the incoming bits and determine the best time
to sample each bit, which is typically the center of the eye (0.5 UI). The CDR’s base Reference Clock(s) is
provided by the PLL. A CDR must be able to track either a fixed phase offset (common clock system) or
small continuous phase offset (non-common clock system), between the incoming data/clock and the
CDR’s base clock. Jitter on the base CDR clock and/or the incoming data stream can cause bit sampling
errors to occur.
Although not explicitly mentioned in the PCI Express Base Specification, Revision 2.0 , Receivers may
implement some form of Receiver equalization, to help compensate for the Channel's low-pass
characteristics. In general, Receiver equalization only needs to be used on longer Channels.
1.1.2.1 Receiver Equalizer Registers – 8-Port Mode
The PEX 8632 provides a programmable Receiver Equalization function. Ports 0 and 4 each have a set of
Receiver Equalizer registers, located at offsets BA4h and BA8h, to control a group of 16 SerDes. Each
individual SerDes has a 4-bit control word. Table 1 describes the Receiver equalization effects.
Table 1. Receiver Equalization Settings
SerDes N Receiver Equalizer[3:0] Equalization
0000b Off
0010b Low
0110b Medium
1110b High
1.1.2.2 Receiver Equalizer Registers – 12-Port Mode
The PEX 8632 provides a programmable receive equalization function. Ports 0, 4, and 8 each have a set
of
Receiver Equalizer registers, located at offsets BA4h and BA8h, to control a group of SerDes. Ports 0
and 4 each control 12 SerDes, and Port 8 controls 10 SerDes. Each individual SerDes has a 4-bit control
word.
Table 1 describes the Receiver equalization effects.