1.1
PCI Express Link Interface
PLX’s PEX 8632 is a 32-Lane, 8- or 12-Port
PCI Express 2.0
(
that is
, Gen2)-compliant switch.
PCI
Express 2.0
supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer
for each Lane is implemented as a SerDes transceiver, which is composed of a transmit path and receive
path. The transmit path typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic
(CML) driver. The receive path consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR),
and a de-serializer.
Note:
The PEX 8632 can be operated in 8- or 12-Port mode. For complete details, refer to the PEX 8632
Data Book.
As the
PCI Express Base Specification, Revision 2.0
, continues to mature, so does its description of the
Physical Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components –
Transmitter, Receiver, Reference Clock, and Channel. The Transmitter and Receiver elements are
typically integrated into PCI Express silicon. The Channel and Reference Clock are implemented at the
system level. The PCI Express interoperability matrix implies that all four elements must support 5.0 GT/s
for the Link to successfully run at 5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not
be able to operate beyond 2.5 GT/s. Another important concept is that 2.5 GT/s is
not
a subset of
5.0 GT/s. This implies that a design targeted to meet 5.0 GT/s might not successfully run in a 2.5 GT/s
environment, if those design criteria are not met, as well.
illustrates a block diagram of a sample PCI Express Link.
PLL1
CDR1
PLL2
CDR2
RefClk
Rx1
Rx2
Tx1
Tx2
Channel
Channel
Device 1
Device 2
Figure 1. Sample PCI Express Link Block Diagram
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
2
© 2007 PLX Technology, Inc. All Rights Reserved.
